Has anyone successfully integrated a simulation testbench with the altera_mem_if_ddr3_emif Megawizard into their own design (different port size/width/etc)?Following the Altera guidebook (EMI_DG_009-5.1) was fairly straight forward... When I try to simulate DDR3 interface with our own design, I realize the top block invoked the DDR3 interface which has different width/bit **Warning: (vsim-8684) No drivers exist on our port /U0/U0/afi_clk, and its initial value is not used. afi_clk is the PHY Clock generated from the memory controller, I can never see afi_clk or local_init_done been driven in ModelSim, it probably means I am not pointing to the library correctly, or not using the right model. Is there a separate file (e.g. .vho) I should be aware of when performing DDR3 simulation? I was able to locate the .vho for all other Megawizard created modules (PLL, etc) except DDR3. Many thanks for the help!!
The mismatch in Avalon port can be resolved by re-generating the core and re-generate example design once more. I found the equivalent model at the example design: <DDR3 TOP>_example_sim_e0_if0.vhd, all we have to do is copy all the associate files into the library and replace it to the <DDR3 TOP>.vhd in my own design to run functional simulation.