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Altera_Forum
Honored Contributor I
955 Views

DDR3 SDRAM Controller - issues caused by enabling the Efficiency Monitor !!!

Hi guys :) 

 

Another thread about the DDR3 SDRAM Controller with UniPHY... 

Used Quartus version is 13.1 SP1.  

 

I have built and run a memory test design with QSYS with the aim to do some latency and efficiency tests. 

The memory test template and my selfmade implementation where both successful. Today I tried the EMI-Toolkit to check the calibration status of the controller (Debugging Option: Option 1 in the "Diagnostic" tab) and I had no problems doing so.  

 

but, then I decided to enable the "Efficiency and Protocol Checker" of the DD3 SDRAM Controller in the tab "Diagnostics", which cause a lost of the Avalon Slave port for the User Logic to access the data of the RAM! The "Efficiency and Protocol Checker" should enable the possibility to track the efficiency and command errors, which is a nice feature. 

 

Q1: How should the "Efficiency Monitor" calculate the efficiency when the user is not able to perform accesses to the memory!? 

Q2: And what does the warning: "Warning: ddr3_emif: in composed mode interface avl_0 must be an export of an internal interface" mean?? (I asked google but even he was felt sorry to refuse my question ;) ) The documentation just says: "Enable efficiency measurements to be performed on the controller avalon interface" so why is it disabled for the User Logic? 

 

For me it looks like a bug and I checked a lot of documents to find a explaination for this behaviour. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=9339  

 

Q3: Another questions arises: Why is it possible to enable the EMIF On-Chip Debug Toolkit with the checkbox, when it is enabled by selecting the "Debugging feature set: Option 1" ? 

Maybe it would allow the user the access the calibration registers via the the Avalon Slave Port or JTAG to read the content of the registers. 

 

Q4: When I enable the "EMIF On-Chip Debug Toolkit" with Avalon-MM Slave (without enabling the efficiency monitor, otherwise I couldn't see the Slave Port), the address span is huge from 0 to 0xf_ffff... In the document "Functional Description—UniPHY" on page 34, there is a list of the "UniPHY Register Map" and the "Controller Register Map" with an address span of 0 to 0x123...  

 

Q5: When I enable the "CSR" with Avalon-MM Slave, the address span is also huge from 0 to 0x3_ffff. In the document "Functional Description—UniPHY" on page 44, there are registers just from 0 to 0x50 listed ( Avalon CSR Slave and JTAG Memory Map ) !?  

 

 

I tried all combinations of the Controller Settings and Diagnostic tabs, but the Avalon Slave port for accessing the RAM is hidden depply in the tcl-waste land of the controller and I think this problem is not quite common. 

Generally I just want to do some efficiency measurements. In first approach I would like to do it with the EMIF Debug Toolkit, to save time and implemention effort. 

 

Hopefully someone could help me with this problem! I am counting on you ;) ! 

 

Kind regards, 

Roland
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Altera_Forum
Honored Contributor I
54 Views

Hi All! 

 

So problem solved... Yeah not really it is a known issue: 

 

Q: Efficiency Monitor Not Usable With Arria V or Cyclone V Hard Memory Interface - Solution ID: fb107818; Not yet fixed! 

Workaround / Fix 

 

The workaround for this issue is to use Qsys to generate the external memory interface IP without the Efficiency Monitor, and then generate the Efficiency Monitor separately. You can then enable the Efficiency Monitor for your interface by connecting the Avalon interfaces manually. 

 

This issue will be fixed in a future release. 

 

Q: IP Generation Fails When Both Efficiency Monitor and Ping Pong PHY Enabled - Solution ID: fb158297 

Workaround / Fix 

 

The workaround for this issue is as follows: 

 

In Qsys, manually instantiate your UniPHY-based external memory interface IP with Ping Pong PHY enabled and the Efficiency Monitor and Protocol Checker disabled. 

Instantiate two copies of the Efficiency Monitor and Protocol Checker and connect them to the avl_c0 and avl_c1 interfaces of the UniPHY IP. 

 

This issue will be fixed in a future version. 

 

 

I hope others facing the same problem will now be able to find the reason a bit faster! 

Solution is just to instantiate the Performance Monitor: "Altera Avalon-MM Efficiency Monitor and Protocol Checker" between the Data_master of the Nios, in my case, and the Slave Port of the SDRAM Controller. 

 

 

I let you know if this solution leads to the good results. 

 

Au revoir. 

Roland
Altera_Forum
Honored Contributor I
54 Views

Hi again, 

 

I placed the "Altera Avalon-MM Efficiency Monitor and Protocol Checker" in my QSYS Design, et voi lá, it is now possible to create a memory efficiency statistic. 

Now I have to write a programm which allows to make resonable statements, according to throughput, latency and efficiency. Currentely I am running a March -C mem test and some pattern transfers with a DMA on the RAM.  

Finally I want to be able to give a prediction about the real-time ability of the Controller.  

 

Kind regards, 

Roland
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