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DDR4 pin placement - Stratix 10 Tx

I am facing the following error during the fitter stage of design with emif ip

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints . Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175011): Conflicting region assignments found for DQ_GRP, which is within External Memory Interfaces Intel Stratix 10 FPGA IP emif_test_ip_altera_emif_s10_1923_ajeo6ya
Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.

I have refered the pin details sheet and based on that assigned DDR4 pins.

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