Can the TSE IP block configured for 100/10MB run from OnChip Ram only?
Do I have to include MSGDMA interfaces?
Is there a document explaining how to configure platform designer to produce the hw layer for the Simple Socket Server template?
I can only find example code which when I modify it either wont build or builds and wont run or crashes when it runs. I cant find documentation that explains what are the expected minimum Platform Designer requirements for making the Simple Socket Server project template in Nios II software build tool work. I am using Quartus prime lite V18.1 but could switch to a newer version if needed.
I have a MAX1000 board to which I have connected a DP83848 evaluation board.
Hope this message find you well, unfortunately as we do not receive any further on clarification provided. Hence, this thread will now be transitioned to community support. If you have new queries or further query on this thread, please feel free to open a new thread or reopen this thread to get support from Intel experts. Otherwise, the community users will further help you with doubts in this thread.