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Altera_Forum
Honored Contributor I
718 Views

DMA read using PCIe hard core

We design DMA controller which implement the data transmission between the PCIe module(which is PXI device) and general PC(OS is Windows XP). The Quartus version is 11.0, and the FPGA is EP4SGX70HF35I3. We use the HARD IP for PCIe, ×4 lanes, Native endpoint.  

 

We already implement DMA write(transfer data from FPGA to PC through memory write request TLP) successfully. Now we meet some question in implementation of DMA read. The question is as follows : we configure memory read request TLP and read data from PC's memory, but cannot receive memory read completion TLP with data through RX port. Does the native endpoint could implement the DMA read? Or we should initiate a rootpoint? Or we configure the TLP in a wrong way? 

 

 

Thanks for your answers.
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4 Replies
Altera_Forum
Honored Contributor I
18 Views

 

--- Quote Start ---  

 

Does the native endpoint could implement the DMA read? Or we should initiate a rootpoint? Or we configure the TLP in a wrong way? 

 

--- Quote End ---  

 

PCIe end-points can implement both DMA reads and writes, you do not need to implement a root-complex (in fact you cannot if the board is to be plugged into a peripheral slot). 

 

You must have an error in your logic. 

 

I'd recommend simulating your design, but Altera's support for PCIe simulation is not particular good. I haven't tried recently (Quartus 13.x), so perhaps it has improved. Hopefully others on the forum will comment. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
18 Views

Thanks a lot. 

Then, do you know some Doc about the PCIe DMA using Altera hard IP, especially the DMA read. 

 

 

--- Quote Start ---  

PCIe end-points can implement both DMA reads and writes, you do not need to implement a root-complex (in fact you cannot if the board is to be plugged into a peripheral slot). 

 

You must have an error in your logic. 

 

I'd recommend simulating your design, but Altera's support for PCIe simulation is not particular good. I haven't tried recently (Quartus 13.x), so perhaps it has improved. Hopefully others on the forum will comment. 

 

Cheers, 

Dave 

--- Quote End ---  

Altera_Forum
Honored Contributor I
18 Views

 

--- Quote Start ---  

 

do you know some Doc about the PCIe DMA using Altera hard IP, especially the DMA read. 

--- Quote End ---  

 

Sorry I do not.  

 

I analyzed the Altera Qsys PCIe end-point design in this thread: 

 

http://www.alteraforum.com/forum/showthread.php?t=35678 

 

but the end-point bus master interface was not suitable for my application. Rather than spend time to develop my own PCIe IP at the TLP level I used a PowerPC processor with PCIe for my PCIe interface and put the FPGA on its local bus. 

 

I'd recommend looking at whether Altera has PCIe simulation support now, and if they do not, post a new thread asking people to recommend PCIe simulation IP from a third party.  

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
18 Views

The PCIe core is really missing a dma engine. 

If you need to tranfser to/from arbitrary physical addresses you have serious problems. 

 

I have wondered about how difficult it would be write a dma engine that could transfer from a dual-ported M9K block into the Avalon slave interface of the PCIe block, and specify a full 64bit address (well as many bits as the target host uses, IIRC 36 for x86 cpus). 

In many cases the rest of the system could arrange to use that memory block.