We wish to perform c = c + (a * b) where,
a, b and c are 32-bit unsigned numbers.
Please let us know how best to implement this multiply-accumulate in Verilog so that the DSP blocks available in Stratix 10 can be utilized to achieve the highest Fmax possible.
We are okay with either fixed / floating point numbers not necessarily unsigned if that will help achieve higher Fmax (but the data width is 32 bits).
We also don't mind the latency in terms of any number of clock cycles from input to output.
Thanks for the reply.
We modified our Verilog code and introduced registers at the appropriate places by looking at the circuit diagram of the 'Native Fixed Point DSP Intel Stratix 10 FPGA IP'. The latency from input to output is 5 clock cycles with the modified code. Now, Quartus is saying that all the DSP blocks, that it is inferring, are fully utilizing the recommended internal register banks.
Please find the modified MAC unit Verilog code:
Please do suggest further improvements, if any, to achieve higher Fmax.