FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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DSP Builder Signal Compiler Error

Honored Contributor II

I have a model that gets all the way through the compilation and programming process but then freezes after the message that the programmer action is complete. I have left it at this point for 2.5 hours with no change and I have no idea what could be causing it. I have been able to program simpler designs with no problem but as soon as I put an FIR megablock in the model I get this error.

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