Debugging failed DMA

[UserID4331231]

Hello Everyone

I am using Agilex7 FPGA. I am using Multi Channel DMA FPGA IP for PCI Express - Data movers only Example design and have modified example design to fit into my needs. 

BAR0 is 16KB - In lspci I can sees that BAR 0 starting offset is 9600_0000h

Internally I have a AVMM FIFO, its write port (512 bits - 64bytes) is connected po_h2ddm_master port with address mapping of 40h to 7fh   

For initial testing I want to move 64 byte from host side memory to device internal FIFO .

so, I am choosing  My src_addr as 9600_0000h and dest_Addr as 40h.

From Signal Tap analysis I can see that my custom RTL is sending h2d descriptor as per description in link below. 

https://www.intel.com/content/www/us/en/docs/programmable/683821/25-1-1/h2d-descriptor-format-h2ddm-desc.html 

H2D descriptor I sent  is as following 

[255:192] - 0000_0000_0000_0000h

[191:128] - 0020_8000_0000_0040h

[127:  64] - 0000_0000_0000_0040h

[63   :    0] - 0000_0000_9600_2000h   

The response I am getting h2ddm-desc-status interface tell me that DMA has failed as bit 19 is set to  '1'. H2D_Desc_status I am getting is 0008_0000h.

https://www.intel.com/content/www/us/en/docs/programmable/683821/25-1-1/h2d-descriptor-status-h2ddm-desc-status.html  

I need help debugging failed DMA. I can reproduce this easily.  The documentation says "CISE to elaborate on error condition". What does CISE mean? how do I get more details on Why DMA is failing ? 

[UserID4331231]

there is typo above and I cant edit the post so adding fix here.  "so, I am choosing  My src_addr as 9600_2000h and dest_Addr as 40h."

Also the reason I am using 9600_2000h address as this address is mapped to BAR0 and I have preloaded BAR 0 with known patterns. So my intention is to use DMA to read some data from BAR0 memory to internal FIFO.  And next step is to read FIFO internally and confirm the pattern.