Delay in SPI-to-Avalon-MM IP Response After MAX10 Reset

[chrisssynco]

Hello everyone,

I’m using the SPI-to-Avalon-MM IP to enable communication between an external microcontroller (MSP430) and a MAX10 FPGA (MAX10M50DAF256CG). In my setup, the microcontroller acts as the SPI master, and the FPGA is the slave.

The microcontroller also controls a GPIO line connected to a load switch, allowing it to power the MAX10 on or off. The FPGA receives a 26 MHz external oscillator input, which feeds into a PLL. The PLL’s lock signal is used to generate a system reset.

Here’s the behavior I’m observing: even after the PLL lock signal asserts and the system leaves reset (measured by routing the lock signal to an external FPGA pin and timing from the moment CONF_DONE goes high), it still takes around 9 ms before the FPGA and the SPI-to-Avalon-MM IP start responding to SPI messages from the microcontroller.

My questions are:

• What could be causing this post-reset delay?

• Is there a defined startup time for the FPGA and IP to begin responding?

• I haven’t found documentation on this—are there any relevant resources?

Thanks in advance for your help.

[ShengN_Intel]

Hi,

That duration after CONF_DONE signal rising is for device initializing (Initializes internal logic and registers && Enables I/O buffers) before enter user mode if check this document https://cdrdv2-public.intel.com/666495/ug-683865-666495.pdf page 30,32:

The initialization sequence begins after the CONF_DONE pin goes high. The initialization clock source is from the internal oscillator and the MAX 10 device receives enough clock cycles for proper initialization.

Thanks,

regards,

Sheng

[chrisssynco]

The time it takes for the PLL to lock is quick - a consistent 248 us. But shouldn't it be the case that the device should be good to go after the lock signal going high? The device takes much longer to function after this lock signal going high - on the order of milliseconds.

[ShengN_Intel]

Hi,

Do you mean 9ms delay after CONF_DONE? If yes, most likely not because of the initialization because the max CONF_DONE high to user mode delay for max 10 is just 605us.

Possible signal tap the design waveform for taking a look?

Thanks

Regards,

Sheng

[ShengN_Intel]

Hi,

Another thing is that could you confirm that the 9ms delay measure not include the internal configuration time? Because internal configuration time will possible take until 9ms if check this document https://cdrdv2-public.intel.com/666495/ug-683865-666495.pdf table 7. Internal configuration time is from nSTATUS goes high to CONF_DONE goes high.

Thanks,

Regards,

Sheng

[ShengN_Intel · Accepted solution]

Hi,

Let me know if you have any further update or concern?

Thanks,

Regards,

Sheng

[chrisssynco]

Sorry. I figured out the issue and its unrelated to the FPGA. Thanks.