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DisplayPort IP Sink - Spread Spectrum Clocking

Honored Contributor II

Hey can anyone comment if the Altera displayport receiver (sink) IP core supports spread-spectrum clocking, by the display port source, of the incoming video lanes? 


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Honored Contributor II

Are you looking at the Bitech Displayport IP core. 


I don't know for sure, but this should be more of a function of the FPGA PLL than the logic core. Basically can the core PLL maintain lock when the input clock is spread. 


I would check the specific family of FPGA handbook and check the PLL capablilites. I know SATA also can use spread spectrum clocking, and some families for FPGA are ok with this while others are not. 


Honored Contributor II

Anakha, thank you. Per your suggestion I began review of the Arria data. It does appear Arria family Giga bit receiver PLLs have capability to accept the extra jitter from SSC. Also appears that PCI-e transmitters can use SSC, similar to the DisplayPort spec, and Arria devices appear to have good PCIe support. So gonna take a bit more research but looks promising. Yes the Bitec core as well as the Altera core are under consideration for our solution. --kb