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DisplayPort Only Connects to Windows not Linux

DZuck1
Novice
8,007 Views

Hi,

 

I am trying to use the DisplayPort sample design on a Stratix 10 board. I have implemented the exact sample project from Intel with the Bitec daughter card but am seeing some issues.

 

When I plug a Windows PC (7 or 10) into the daughter card it immediately performs the link training and connects to the Operating System. Using SignalTap I can see data flowing out of the Clkrec core (VSYNC, HSYNC, DE, Data). When I plug in a monitor to the TX port I can see a windows desktop as if it were a second monitor to my Windows PC desktop.

 

When I plug a linux machine (or same hardware but dual boot) into the DisplayPort RX port, Linux recognizes the DisplayPort sink as a monitor. However I am not seeing any data come out of the Bitec Clkrec.

 

Linux is reporting that it found valid modes for the DisplayPort monitor.

 

Can you help me figure out why the DisplayPort core has no trouble connecting to Windows but has trouble connecting to Linux?

 

Setup:

OS: CentOS 6

Graphics Card Vendor: NVIDIA

DisplayPort Core: GPU mode enabled, AUX debug enabled, core is set for HBR3 and 4k60 resolution.

Tool: Quartus 19.1

 

Thanks!

Daniel

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DZuck1
Novice
2,690 Views

Hi dlim,

 

The v20.2 project compiled and I loaded it onto my board.

 

I am seeing that on the Win10 machine it never locks but it does lock on the Win7 machine. Unfortunately, I do not see any picture on the monitor I plug into the TX port on the bitec daughter card. I have attached the MSA dump traces for win7 and Win10.

 

Thanks,

Daniel

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DZuck1
Novice
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I am not sure if it is relevant, but I had to unbond the TX lanes due to the layout of the FPGA board. The transceiver lanes are not in order going to the FMC connector and Quartus would not let me compile when they were bonded like in the sample design.

 

This change only affected the TX PHY IP core and not the RX PHY IP core.

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SZack
Partner
2,683 Views

Hi Deshi,

Do you have any feedback for Daniel?  Anything else you would like him to test or provide additional feedback on?

Thanks,

Steve Zack

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DZuck1
Novice
2,678 Views

Hi dlim,

 

I tried out the RX only design in Win7 and Win10 (did not have a chance with Ubuntu or CentOS). Win7 seemed to lock and finish link training but Win10 did not.

 

Attached are multiple MSA dumps for each.

 

Thanks,

Daniel

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DZuck1
Novice
2,671 Views

Hi Deshi,

 

Attached are the logs for Ubuntu and CentOS with the RX only design. Ubuntu did not complete LT at all (the OS refused to connect to it) and CentOS tried to connect but had lots of trouble (CR Done sometime F and SYM was usually 0). 

 

In CentOS, I modified the /etc/X11/xorg.conf to set the "ConnectedMonitor", "UseDisplayDevice" and "CustomEDID" switches to force Linux to talk to the DP RX core. I could see the LED toggling but never converge. Linux locked up while this was happening.

 

Thanks,

Daniel

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DZuck1
Novice
2,670 Views

I have also confirmed that both GPUs are set to 8 bpc / 24 bit color.

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DZuck1
Novice
2,668 Views

I forgot to mention that I needed to add a clock control IP to the design because the fitter did not like that the same clock (refclk_p) was going to an IOPLL and an ATXPLL,

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Deshi_Intel
Moderator
2,662 Views

Hi Daniel,

Attached is some of status signals that we can use in signal_tap for link training debug.

Regarding your enquiry on unbond channel

  • Using unbond option will increase the skew between 4 DP channels. It's not recommended option but I am not sure is there anything else that you can do on your board since the connection is fixed ?
  • I think DP Tx HBR2 has lane to lane output skew spec of 4UI + 500ps   

For sharing clock source pins on IOPLL and ATX PLL

  • Using clock control IP meaning you are using FPGA core clock instead of dedicated clock source from FPGA IO pins directly. Again, not recommended due to higher jitter impact

Anyhow, although these design change is bad but we are not sure whether it's related to your original no video output issue. I still feel it's related to GPU interaction with OS level issue.

Regards,

dlim 

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DZuck1
Novice
2,656 Views

Hi dlim,

 

I was able to get the SignalTap file to compile as is in my v20.2 project and with a change to the RX_PHY gxb_rx_Clkout clock in my v19.2 project.

 

Is there any specific signal I should be triggering on?

 

Thanks,

Daniel

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SZack
Partner
2,646 Views

Good morning Deshi,

Can you please let Daniel know what signals he should be looking at in SignalTap? 

Thanks,

Steve

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Deshi_Intel
Moderator
2,701 Views

Hi Daniel,


I understand that your system setup is like below :

------------

system setup

------------

GPU -> DP cable -> Bitec DC rev11 -> custom board (S10 SX280 FPGA) -> same Bitec DC rev11  -> DP cable -> Monitor


Lets' stick with using Intel FPGA DP default example design for debug purpose. Don't integrate with additional design block for now to keep thing simple.

  • Quartus version : v19.2 (I am thinking v19.2 since you mentioned it started support Bitec DC rev11 as compared to not supported v19.1)
  • DP IP bpc : 8 bpc
  • DP data rate setting : 5.4G (HBR2)
  • GPU mode : turn on GPU mode is fine


After that, share with me the MSA log for Nvidia GTX 660Ti running in Linux.


For my side, I will try to check for some transceiver Rx channel internal status signal that you can add to signal_tap to aid in debug purpose.


Thanks.


Regards,

dlim


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DZuck1
Novice
2,692 Views

I removed my entire project and only used the sample project (v19.2) with my pinout.

 

With both Win7 and Win10 I am seeing the same issue I had before where LT goes and goes and goes until the NIOS/UART gives out (unresponsive).

 

I was able to grab this MSA dump right before it stopped:

 

------------------------------------------
------ TX Main stream attributes -----
------------------------------------------
--- Stream 0 ---
MSA lock : 0
VB-ID : 19 MISC0 : 00 MISC1 : 00
Mvid : 138E5 Nvid : 8000
Htotal : 0000 Vtotal : 0000
HSP : 0000 HSW : 0000
Hstart : 0000 Vstart : 0000
VSP : 0000 VSW : 0000
Hwidth : 0000 Vheight : 0000
CRC R : 0000 CRC G : 0000 CRC B : 0000
--- Stream 1 ---
MSA lock : 0
VB-ID : 00 MISC0 : 00 MISC1 : 00
Mvid : 0000 Nvid : 0000
Htotal : 0000 Vtotal : 0000
HSP : 0000 HSW : 0000
Hstart : 0000 Vstart : 0000
VSP : 0000 VSW : 0000
Hwidth : 0000 Vheight : 0000
CRC R : 0000 CRC G : 0000 CRC B : 0000
------------------------------------------
-------- TX Link configuration -------
------------------------------------------
Lane count : 4
Link rate : 5400 Mbps
------------------------------------------
------ RX Main stream attributes -----
------------------------------------------
--- Stream 0 ---
VB-ID lock : 0 MSA lock : 0
VB-ID : 19 MISC0 : 00 MISC1 : 00
Mvid : 0100 Nvid : 0000
Htotal : 0000 Vtotal : 0000
HSP : 0000 HSW : 0000
Hstart : 0000 Vstart : 0000
VSP : 0000 VSW : 0000
Hwidth : 0000 Vheight : 0000
CRC R : 0000 CRC G : 0000 CRC B : 0000
--- Stream 1 ---
VB-ID lock : 0 MSA lock : 0
VB-ID : 00 MISC0 : 00 MISC1 : 00
Mvid : 0000 Nvid : 0000
Htotal : 0000 Vtotal : 0000
HSP : 0000 HSW : 0000
Hstart : 0000 Vstart : 0000
VSP : 0000 VSW : 0000
Hwidth : 0000 Vheight : 0000
CRC R : 0000 CRC G : 0000 CRC B : 0000
------------------------------------------
-------- RX Link configuration -------
------------------------------------------
CR Done: F SYM Done: 0
Lane count : 4
Link rate : 5400 Mbps
BER0 : 7FFF BER1 : 08A8
BER2 : 072A BER3 : 17A6

 

I am now compiling with v20.2 to see if it works any better.

 

Thanks,

Daniel

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Deshi_Intel
Moderator
2,554 Views

HI Daniel,


I am setting this forum case to closure since we have moved into private debug discussion.


Thanks.


Regards,

dlim


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