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Doing a 32-bit access through an Avalon 32-bit Bridge to a 16-bit wide Avalon MM SDRAM Controller slave doesn't seem to follow the Avalon Dynamic Bus Sizing in my QSYS design.

CPope
Beginner
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Kenny_Tan
Moderator
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Can you send us screenshot showing it? ​

CPope
Beginner
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Hello,

Did you receive the 3 .png files that I uploaded?

 

I am using Quartus Prime v15.1.

I have a proprietary 32 bit RISC design at the top level of the FPGA. The CPU accesses at 32 bit Qsys design through two 32 bit External to Avalon Master MM bridges. I am just using one of the bridges right now.

A screenshot of the Qsys design was attached and uploaded and called qsys_design.png. The Qsys design has an internal 16-bit wide SDRAM Controller slave. The FPGA and board design just have a single external 16-bit-wide SDRAM.

 

Running the design with pre-loaded data from a System Console (and Jtag Master) I have two SignalTap png files. The first one shows the bus activity (outside of Qsys) at the FPGA top level. The accesses are just 32 bit reads. The second SignalTap png file is zoomed in to show the 32 bit data presented at the top-level Qsys port for address 0x0000125C at the time when the "acknowledge" signal is active.

 

My understanding with the Avalon Bus Dynamic Bus Sizing is that the Avalon Bus Fabric will to the conversion to 32 bits. Each 32 bit read from thew Qsys design will cause the SDRAM Controller to do two 16 bit reads to the SDRAM and then the sequential 16 bit half-words will be constructed into a single 32 bit word when the "acknowlledge "is activated.

 

However, as the zoomed-in SignalTap activity illustrates the Qsys 32-bit port just has two identical 16 bit half-words as part of the 32 bit data.

 

I use this same SDRAM Controller in other qsys designs that employ an internal Qsys-based NIOS 32 bit CPU and there is no problem.

 

Is there some enable option not set in my current design?

 

Thanks for your time on this matter,

 

Charles

 

 

Kenny_Tan
Moderator
404 Views

There are no screenshot attached, can you reattached it?

 

Did your ​SDRAM Controller design with a byte enable?

 

Avalon-MM moves data in the form of symbols using addresses to determine destination

-Symbols are typically bytes (i.e. 8 bits)

-Masters cannot access slaves of a different symbol size

-Without master byte enables Qsys assumes master is always accessing full words

 

 

CPope
Beginner
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Hello KTan, Here is a zoomed out view of the SignalTap capture: Below in the zoomed-in view you can see the 32 bit data at the Qsys Port presented at the top level of the FPGA design. The Bus Cycle is being held until completion by the Qsys "External to Avalon Bridge" by using the "acknowledge" signal. When it is asserted you can see that the Qsys design has merely duplicated the 16 bit value on the lower part of the data bus to the upper part of the data bus. I was expecting the Qsys Avalon fabric to do the Dynamic Bus Sizing (as explained in the Avalon Bus Spec). I was expecting the Qsys Avalon fabric to do the Dynamic Bus Sizing (as explained in the Avalon Bus Spec). Here are some further screenshots of my Qsys Design: This is the Bridge Master with the 4 Byte Enables, 32 bit data width: This is the SDRAM Controller Slave: This is the QSYS design showing the internal mm interconnections hookup: I appreciate your prompt attention to this matter. Charles On 2018-09-05 22:19, Intel Forums wrote: Links:
CPope
Beginner
404 Views

Hello,

This is another attempt to send you a pdf of my earlier email responses. The pdf discussed earlier is attached.

Charles

 

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