Tool = Quartus Pro 2019.1, ModelSim 10.6d (subscription edition) FPGA Component = Stratix 10 (1SX280LU2F50E2VG)
I am running into a problem with the simulation of example design for the Low Latency Ethernet 10G MAC IP. I created an IP component using an example design preset for the IP as below. I then generate the example design for this IP.
10M/100M/1G/2.5G/5G/10G USXGMII Ethernet with 1588 Example Design (Stratix 10)
I open ModelSim and change directory to <example_path>/simulation/ed_sim/mentor. Then I type "source tb_run.tcl" in the transcript window. Intel User Guide 20073 explains this process (section 1.3). The script begins running for a while and then I get the following error.
I've searched online for solutions and found some. I've tried the following:
Anyone have any other suggestions? I tried two other presets in the IP and they all fail at exactly the same point and exactly the same SV file.
I am able to simulate the design example though. Not sure if this works, one suggestion is make sure that the path does not have any empty space in between. e.g. C:\project example -> C:\project_example.
Yes, I did also check that there are no spaces in the path. To be sure I did regenerate the example project this morning and placed it directly on C:/ as shown.
I still get the error. Always the same file.
** Error: (vlog-7) Failed to open design unit file "../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_eth_1588_tod_10g/altera_merlin_slave_translator_191/sim/address_decoder_channel_eth_1588_tod_10g_altera_merlin_slave_translator_191_x56fcki.sv" in read mode.
I also tried generating it in the latest version of Quartus (20.2 Pro) and still get the same error. I am running Windows 10. You running the same? Do you have "LongPathsEnabled" in the Windows registry?
You followed the same steps?
1) generate the example project
2) start ModelSim
3) change directory to C:\EXAMPLE_DESIGN\LL10G_10G_USXGMII_1588v2\simulation\ed_sim\mentor
4) type source tb_run.tcl
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