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HBhat2-GRL
New Contributor I
294 Views

Electrical IDLE entry & exit detection on receiver side of the transceiver

Hi,

 

I am working on Arria 10 Transceiver for a custom protocol and I need to put the transmitter in electrical IDLE as per the protocol.

On the transmitter side, I can put transmitter in electrical IDLE using tx_pma_elecidle port.

 

On the receiver side, I need to detect the electrical IDLE. I am thinking to use CDR status status "lock to data & lock to ref" ports.

 

I understand that whenever transmitter is active both lock to data & lock to ref are asserted (1). Whenever the transmitter goes into electrical IDLE, the lock to data status in the corresponding receiver in the other side goes low (de-asserted) and receiver will continue to lock to ref only. Whenever the linked transmitter exits electrical IDLE, the CDR status of the receiver (lock to data) asserted again.

 

In this way I am planning to detect the electrical IDLE entry & exit in the receiver side. Please clarify whether my understanding is correct or not.

 

With regards,

HPB

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10 Replies
CheePin_C_Intel
Employee
256 Views

Hi HPB,

 

As I understand it, you have some inquiries related to using RX CDR LTD status to detect when the TX is being put into electrical idle. For your information, the CDR might take some time before it lose lock to data and de-assert the LTD. I would like to recommend you to explore into using the rx_std_signaldetect signal to detect the TX electrical idle. Whenever the TX is in elecidle, there should be no valid signal arrive at the RX. The RX signal detect will de-assert. Note that you would need to configure the signal detect threshold to the right settings to ensure normal operation of your link. 

 

For your reference, as per the A10 user guide, in SATA application, the following values are used:

 

For SR: sd_threshold for SATA = SDLV_4

For LR: sd_threshold for SATA = SDLV_6

 

Also, you would need to have 8b10b block enabled when you are using this signal detect.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

HBhat2-GRL
New Contributor I
256 Views

Hi @cheepinc_Intel​ ,

 

Thanks for the response & options.

rx_std_signaldetect : This port is accessible when I select PCIe configuration. In my development, I am using Basic (Enhanced PCS) mode as I am writing my own custom PCS for the protocol. So, I think rx_std_signaldetect may not be useful for me.

 

One more thing, whether is it possible to use rx_data_valid port for the same purpose (to know whether the connected TX is in electrical IDLE or not) ?

 

With Regards,

HPB

CheePin_C_Intel
Employee
256 Views

Hi HPB,

 

Thanks for your update. As I understand it, you are using Enhanced PCS and thus the rx signal detect feature is not available. In this case, you may use the CDR lock-to-data status to tell if the TX has gone into electrical idle state. Additional info to share is that the CDR lock-to-data status will toggle when there is no valid data. Only when the assertion remain high for more than 4us would indicate the CDR has achieve LTD.

 

Regarding the RX data valid signal from the FIFO, this is part of the FIFO which is after the CDR. Thus, I think using CDR lock status would be more appropriate.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

HBhat2-GRL
New Contributor I
256 Views

Hi,

 

"

I understand that whenever transmitter is active both lock to data & lock to ref are asserted (1). Whenever the transmitter goes into electrical IDLE, the lock to data status in the corresponding receiver in the other side goes low (de-asserted) and receiver will continue to lock to ref only. Whenever the linked transmitter exits electrical IDLE, the CDR status of the receiver (lock to data) asserted again.

"

That means above understanding is correct & based on lock to data de-assertion & assertion, I can arrive at the conclusion that corresponding TX is in IDLE or not. [Apart from some delay to assert & de-assert the status]

 

With regards,

HPB

CheePin_C_Intel
Employee
256 Views

Hi HPB, Just would like to further clarify on the behavior lock-to-data and lock-to-ref signals: "I understand that whenever transmitter is active both lock to data & lock to ref are asserted (1)." [CP] When transmitter is active and valid data present at the RX, the CDR will achieve LTD mode. The lock-to-data signal will be High. The lock-to-ref signal can be ignored (it may stay at High or toggling) "Whenever the transmitter goes into electrical IDLE, the lock to data status in the corresponding receiver in the other side goes low (de-asserted) and receiver will continue to lock to ref only." [CP] When there is no valid data present at the RX, the lock-to-data and lock-to-ref signals will be toggling. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
HBhat2-GRL
New Contributor I
256 Views

Hi,

 

Thanks for clarification. The toggling may not have any particular duration right? Is it possible to know what is the maximum time the LTD will be high (during toggling LTD will become High for some time & low for some time) although no valid data is present at RX?

 

With Regards,

HPB

CheePin_C_Intel
Employee
256 Views

Hi HPB, Regarding what is the toggling duration of the RX LTD signal, sorry as there seems to be no specific information on this. However, as per my previous note, if the duration of assertion is > 4us, it means that the RX has achieve LTD. This 4us information is available in the user guide -> reset chapter. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
HBhat2-GRL
New Contributor I
256 Views

Hi @cheepinc_Intel​ ,

 

Thanks for pointing towards the reset chapter.

 

Yes, I observed tLTD time (min 4us). As per the reset chapter, if LTD is high for min tLTD time, then it is assured that rx is getting valid data.

 

Also, 5.1.6.2. Lock-to-Data Mode of Arria 10 transceiver user guide,

The rx_is_lockedtodata signal toggles until the CDR sees valid data; therefore, you should hold receiver PCS logic in reset (rx_digitalreset) for a minimum of 4 μs after rx_is_lockedtodata remains continuously asserted.

 

 

With this I can conclude that,

Whenever the link is active, & suddenly if LTD is de-asserted, that means the TX is in electrical IDLE (by considering there is no disturbance to physical channel/connectivity). This is the indication that RX is not receiving valid data. And after some time, if TX comes out of electrical IDLE and starts sending the data, RX side look for the assertion of LTD and monitor that for atleast 4us the LTD gets asserted. If yes, then corresponding TX is out of Electrical-IDLE .

 

 

With Regards,

HPB

CheePin_C_Intel
Employee
256 Views

Hi HPB, Yes, your understanding is correct. Best regards, Chee Pin
CheePin_C_Intel
Employee
239 Views

Hi,


I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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