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Altera_Forum
Honored Contributor I
1,271 Views

Error: Inconsistent I/O type for element "GPIO_0"

Hello  

 

I have the following error when I compile my code: 

 

Error: Inconsistent I/O type for element "GPIO_0" 

 

Could you say me wath is the problem? 

 

I use a Custom IP in SopC for connect a CMOS-Sensor to the GPIO_0. First I would only test my camera, I put the signal in the FPGA and after I get it again to GPIO_1. 

 

I have a DE2-Board with EP2C35F672C6N. 

 

 

 

 

Here my code (toplevel): 

 

-- VHDL Entity CMOS_Sensor_IP_lib.CMOS_Sensor.symbol 

-- 

-- Created: 

-- by - Antonio Carlucci.UNKNOWN (ANTONIOCARLUCCI) 

-- at - 21:11:31 13.10.2010 

-- 

-- Generated by Mentor Graphics' HDL Designer(TM) 2008.1b (Build 7) 

-- 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

USE ieee.std_logic_arith.all; 

 

ENTITY CMOS_Sensor IS 

PORT(  

avs_read : IN STD_LOGIC; 

avs_write : IN STD_LOGIC; 

avs_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 

coe_DATA_IN : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 

coe_FV_IN : IN STD_LOGIC; 

coe_LV_IN : IN STD_LOGIC; 

coe_PIX_CLK_IN : IN STD_LOGIC; 

csi_clk : IN STD_LOGIC; 

csi_reset_n : IN STD_LOGIC; 

avs_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); 

coe_DATA_OUT : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); 

coe_FV_OUT : OUT STD_LOGIC; 

coe_LV_OUT : OUT STD_LOGIC; 

coe_PIX_CLK_OUT : OUT STD_LOGIC; 

coe_SCLK_OUT : OUT STD_LOGIC; 

coe_SDAT_OUT : OUT STD_LOGIC; 

coe_nSENS_RST_OUT : OUT STD_LOGIC 

); 

 

-- Declarations 

 

END CMOS_Sensor ; 

 

-- 

-- VHDL Architecture CMOS_Sensor_IP_lib.CMOS_Sensor.struct 

-- 

-- Created: 

-- by - Antonio Carlucci.UNKNOWN (ANTONIOCARLUCCI) 

-- at - 21:11:31 13.10.2010 

-- 

-- Generated by Mentor Graphics' HDL Designer(TM) 2008.1b (Build 7) 

-- 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

USE ieee.std_logic_arith.all; 

 

LIBRARY CMOS_Sensor_IP_lib; 

 

ARCHITECTURE struct OF CMOS_Sensor IS 

 

-- Architecture declarations 

 

-- Internal signal declarations 

 

 

-- Component Declarations 

COMPONENT IP_Component 

PORT ( 

avs_read : IN STD_LOGIC ; 

avs_write : IN STD_LOGIC ; 

avs_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 

coe_DATA_IN : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 

coe_FV_IN : IN STD_LOGIC ; 

coe_LV_IN : IN STD_LOGIC ; 

coe_PIX_CLK_IN : IN STD_LOGIC ; 

csi_clk : IN STD_LOGIC ; 

csi_reset_n : IN STD_LOGIC ; 

avs_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); 

coe_DATA_OUT : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); 

coe_FV_OUT : OUT STD_LOGIC ; 

coe_LV_OUT : OUT STD_LOGIC ; 

coe_PIX_CLK_OUT : OUT STD_LOGIC ; 

coe_SCLK_OUT : OUT STD_LOGIC ; 

coe_SDAT_OUT : OUT STD_LOGIC ; 

coe_nSENS_RST_OUT : OUT STD_LOGIC  

); 

END COMPONENT; 

 

-- Optional embedded configurations 

-- pragma synthesis_off 

FOR ALL : IP_Component USE ENTITY CMOS_Sensor_IP_lib.IP_Component; 

-- pragma synthesis_on 

 

 

BEGIN 

 

-- Instance port mappings. 

U_0 : IP_Component 

PORT MAP ( 

avs_read => avs_read, 

avs_write => avs_write, 

avs_writedata => avs_writedata, 

coe_DATA_IN => coe_DATA_IN, 

coe_FV_IN => coe_FV_IN, 

coe_LV_IN => coe_LV_IN, 

coe_PIX_CLK_IN => coe_PIX_CLK_IN, 

csi_clk => csi_clk, 

csi_reset_n => csi_reset_n, 

avs_readdata => avs_readdata, 

coe_DATA_OUT => coe_DATA_OUT, 

coe_FV_OUT => coe_FV_OUT, 

coe_LV_OUT => coe_LV_OUT, 

coe_PIX_CLK_OUT => coe_PIX_CLK_OUT, 

coe_SCLK_OUT => coe_SCLK_OUT, 

coe_SDAT_OUT => coe_SDAT_OUT, 

coe_nSENS_RST_OUT => coe_nSENS_RST_OUT 

); 

 

END struct; 

 

 

 

 

 

 

Thanks you for your effort.
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2 Replies
Altera_Forum
Honored Contributor I
119 Views

Hi Antonio, 

I presume that GPIO is the name of the array of your top level pins connecting to the sensor. So you have GPIO[0] which is an input and you are trying to drive GPIO[1] as an output. This is not allowed: all array signals must have the same direction. 

I had a similar case. If this is yours too, simply change the name: i.e. GPIN for GPIO[0] and GPOUT for GPIO[1]. 

 

Cris
Altera_Forum
Honored Contributor I
119 Views

Another option is to make GPIO a bidirectional port and then permanently set [0] as input in your assignments and you will then be able to use the signals one as input and one as an output without spiting the array: 

GPIO <= 'Z'; signalThatUsesGpio0 <= GPIO; GPIO <= outputSignalforGpio1;  

The compile will probably warn you the bidirectional port GPIO[0] is permanently set to an input and GPIO[1] is permanently set to an output, but this is what you want so you can ignore it.
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