Hi, Looking for some help with a NIOS II system running on a DE-5 (Stratix V) board.
I have created a basic NIOS II system which includes just the components to get the system running. I have instantiated an Altsyncram component as a single port read-only memory, and attached it to the Avalon bus associated with the processor. This ROM contains some canned data that I want the NIOS to stream to a custom component. Problem is when I perform a read using the IORD HAL macro, I don't see the data that the ROM was initialized with. However, I can instantiate the In-System memory editor, and the ROM contains the correct data. Alternatively, I can initialize an array in my software program that contains this data, and I have no issue reading from the on-chip RAM being used as the NIOS main memory.
This is a simple system running on a single clock. I used the .sdc file that comes with the DE-5 board, and see no timing failures. The memory is implemented with the block type set to "Auto", although Quartus reports that it is using MLABs to implement memory. Early in the debug process, I set the tool to use M20k blocks for this component, but it didn't seem to make any difference.
Any help would be appreciated, I've been fighting this problem for a while now.
