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5918 Discussions

Error while adding avalon signals in signal tap.

saranya
Beginner
363 Views

Beginner here.

Trying to learn pcie.

I have configured pcie(qsys) with 1 lane and gen2 speed.I have developed a test code,where 256 bytes of data were read and written from/to fpga through pcie. I'm trying to add the avalon signals(address,readdata.read,write etc.,)in signal tap,but I'm getting the following errors.Can somebody help?

Error: The pin driving the input 'DATAIN' of node 'pcie_top:pcie_top_inst|pcie:pcie_inst|altpcie_cv_hip_avmm_hwtcl:pcie_cv_hip_avmm_0|altpcie_cv_hip_ast_hwtcl:c5_hip_ast|altpcie_av_hip_ast_hwtcl:altpcie_av_hip_ast_hwtcl|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf' must have a fanout of 1.
Info: No legal values found

Error: HSSI PMA TX Buffer node 'pcie_top:pcie_top_inst|pcie:pcie_inst|altpcie_cv_hip_avmm_hwtcl:pcie_cv_hip_avmm_0|altpcie_cv_hip_ast_hwtcl:c5_hip_ast|altpcie_av_hip_ast_hwtcl:altpcie_av_hip_ast_hwtcl|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf' is not properly connected on the 'DATAOUT' port. It must be connected to one of the valid ports listed below.
Info: Can be connected to I port of arriav_io_obuf WYSIWYG

 

 

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6 Replies
CheePin_C_Intel
Employee
343 Views

Hi,


Based on the error messages, it seems to be related to the transceiver ports of your PCIe instances not properly connected to transceiver pins. Just would like to check with you if you observe similar compilation error messages without using Signaltap?


Please let me know if there is any concern. Thank you.


saranya
Beginner
339 Views

Hi,

    Thanks for your help.

     No ,I'm not getting those compilation error messages without using signaltap.

 

CheePin_C_Intel
Employee
337 Views

Hi,


thanks for your update. It seems weird as you are signaltap the Avalon signals but error trigger out related to the transceiver pin. Can you please help to create a simple test design with one PCIe instance + signaltap which could replicate the observation? I would like to further look into it. Thank you.


saranya
Beginner
334 Views

Hi,

    As you mentioned, I had  created  a simple design with one PCIe instance only. I compiled the design without adding stp file,it got compiled.I didn't see any error.I face those errors only when I'm adding stp file and then compiling the design.

   Is there any attribute in altera to mark the signals as debug signals in the design?  

  Thanks.

CheePin_C_Intel
Employee
291 Views

Hi,


Thanks for your update. To facilitate the debugging, you can try to add signals to signaltap batch by batch to narrow down which signal is causing the problem. You may then share with me your test design + STP when the problem start to happen.


Please let me know if there is any concern. Thank you.


CheePin_C_Intel
Employee
225 Views

Hi,


As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.



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