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Ethernet MAC

Altera_Forum
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Hello. 

Looking for a free Ethernet MAC controller with MII (10Mbit). Does Altera has it?
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Altera_Forum
Honored Contributor II
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Hi Daixiwen, 

 

Can you please elaborate on your figures? I need to send udp packets at a rate of 60Mbits/sec, however am only getting up to 11Mbits/sec. Are your values for sending using the ethernet benchmarking application? Is your Ethernet making a GbE or 100mbps link?  

 

Is the Nios system capable of sending UDP packets at 60Mbits/sec on a 100mbps link or do I need to focus my attention on a hardware based solution? 

 

Thanks 

D
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Altera_Forum
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I managed to reach about 80Mbits/s on a 100Mbs link. But as said, it required some tweaking... I got the highest speed improvements by putting the packet data in a double port on-chip RAM, and placing key functions from newlib, µC OS and the TCP/IP stack in a tightly-coupled instruction memory. 

And yes, I used the UDP send benchmark for this measurement.
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Altera_Forum
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Daixiwen, 

 

Thats great to know. I was getting high speeds for UDP receive (Board side) but not sending. I am trying everything at the moment to make my design more effecient. I am using basically all the suggestions of the Ethernet Benchmarking Example, however cannot get the c2h compiler working for alt_cksum. I get an error in Nios saying that there are too many connections to the tightly coupled data master, however sopc suggests that it is only packet_memory attached.. so i have to error check that one today. 

 

With regard to placing key funcutions in the tci memory, are you referring to changing the Linker Script memory allocations in system properties of Nios? ie. Program memory -> memory attached to tightly coupled instruction master? 

 

Thanks alot,  

D.
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Altera_Forum
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You can't use the c2h checksum together with a tightly coupled data memory. A tightly coupled data memory can only be connected to one master, and the c2h instantiation would require a second master. You can only have one at a time. 

From my experience, on my design and in my testing conditions, using the c2h checksum was actually slower than doing the checksum in software on a tightly coupled data memory. But this is strongly application dependant. 

Don't forget to compile the software with optimisations! By default in the debug mode there are no optimisations, and the code is really slower. 

 

For the last point, I first profiled the application to see what functions were the most used, and placed them in a tightly coupled instruction memory. For that you first need to add a parameter to the compiler so that it puts each function in a different linker section, and then use a custom linker script to put those sections in the tightly coupled instruction memory. I can try and find out my software project where I did this if you want more details.
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Altera_Forum
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Hi Daixiwen, 

 

My optimisation level is set to -03 and I run as hardware not in debug mode. Is this what you are referring to with optimisation? I am also using the fast packet memory allocation as suggested in the Eth Accelerator example. 

 

I currently have my software running from sram as the cyclone III does not have enough on-chip memory for an Ethernet-based project. It would be really appreciated if you have a project allowing me to place much of the NicheStack into onchip memory. Did you find that the Ethernet part slows down the system or is it Nios and uC/OS in general? 

 

Thank you, 

D
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Altera_Forum
Honored Contributor II
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Yes, this is what I referred as 'with optimisation'. Check that the -O3 option is set for both the application and the system library. 

 

For a strange reason I can't open my project in the NIOS IDE anymore, it can't find it. But looking directly in the project settings files, I found the option. 

You must compile the system library with the -ffunction-sections option. That way each function is compiled in a separate section (.text.function_name). 

Then I adapted the linker script (tci is the name of the memory attached to the tightly coupled instruction memory: 

 

SECTIONS { .tci : { PROVIDE (_alt_partition_tci_start = ABSOLUTE(.)); . = ALIGN(32 / 8); * (.text.cksum) * (.text.asm_cksum) * (.text.irq_Unmask) * (.text.memcpy) * (.text.sosend) * (.text.udp_send) * (.text.ip_write_internal) * (.text.pk_alloc) * (.text.udp4_socksend) * (.text.ip2mac) * (.text.ip_write) * (.text.t_sendto) * (.text.m_freem) * (.text.m_getnbuf) * (.text.udp_maxalloc) * (.text.udp_usrreq) * (.text.tcp_wakeup) * (.text.udp_send) * (.text.udp_alloc) * (.text.m_free) * (.text.udp_maxalloc) * (.text.ip_mymach) * (.text.send_via_arp) * (.text.pk_free) * (.text.tse_mac_raw_send) * (.text.memmove) * (.text.putq) * (.text.pk_validate) * (.text.irq_Mask) * (.text.alt_remap_uncached) * (.text.alt_avalon_sgdma_construct_mem_to_stream_desc) * (.text.tse_mac_sTxWrite) * (.text.alt_remap_cached) * (.text.alt_dcache_flush) * (.text.alt_avalon_sgdma_do_sync_transfer) * (.text.alt_remap_cached) * (.text.getq) * (.text.qdel) PROVIDE (_alt_partition_tci_end = ABSOLUTE(.)); } > tci .text : { *(.text .stub .text.* .gnu.linkonce.t.*) } The tci soction must be listed before the text section. You need to change one line in the .text section, as indicated, to put all the .text.* functions that are not defined in the tci section back in the text section. 

I also noticed that each packet sent generates lots of function calls. I wonder if it would be possible to put the Interniche task stack in a tightly coupled data memory and gain a bit more. 

 

Of course if you still need more speed you can do some UDP communication with hardware, as in the nios2 udp offload example (http://www.nioswiki.com/exampledesigns/nios2udpoffloadexample).
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Altera_Forum
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Where do I add the '-ffunction-sections' setting for the project?

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Altera_Forum
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I don't have the IDE here, but I think it's in the gcc additional build parameters. I'll have a look tomorrow.

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Altera_Forum
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Do a right click on the system library, select properties. Then select the C/C++ Build item, Tool Settings tab, Nios II Compiler, General, and put it in the "Compiler flags" field.

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Altera_Forum
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--- Quote Start ---  

there is already a tse driver in the uClinux port hosted on www.nioswiki.com (http://www.nioswiki.com).  

 

--dalon 

--- Quote End ---  

 

 

Hello, 

have you somebody uClinux running on StratixIII DSP kit with TSE Marvell 88E1111 ethernet chip ?  

Everything looks ok, but don´t work ... 

When i use the  

/>ifconfig eth0 hw ether 00:07:ed:ff:4a:d7 

/>ifconfig eth0 192.168.1.234 

/>ifconfig eth0 up 

/>route add default gw 192.168.1.254 

linux report - Trying 10/HALF - in this moment i don`t know what it does ? 

After this i try ping to ip of my pc, it finish by request timeout (and tx led on board don`t blink).  

Where could be mistake ? The example of webserver (on uC-OSII) work fine and simple socket server too. 

 

Thank you. 

 

Jan Naceradsky, Czech Reublic
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hi Daixiwen, 

Is the Nios system capable of sending UDP packets at 60Mbits/sec on a 100mbps link or do I need to focus my attention on a hardware based solution? 

--- Quote End ---  

 

 

Yes, 60Mbits can easily be done. I can sustain over 900Mbits with UDP on a Cyclone III and TSE and GigE link. I can't see not reaching 90Mbits+ on a 100MB interface. GigE makes a huge difference. Note that at my speeds windows can't keep up. This is with a highly optimized driver, UDP packet generator and a hardware calculated TCP checksum. Without the hardware checksum but using an optimized assembly version I could exceed 500Mbits. 

 

Bill
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Altera_Forum
Honored Contributor II
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Hey BillA, 

 

I am sorry to revive this old thread but i am currently working on a project using the GbE link of a Cyclone V GT Development Kit. I worked through the Simple Socket Server Example and AN440 for accelerating Nios Networking Applications. 

I could only reach about 150-160MBits on the GbE link however. Now I stumbled upon this thread and have some questions regarding the figures you mentioned earlier in this thread. 

 

 

--- Quote Start ---  

Yes, 60Mbits can easily be done. I can sustain over 900Mbits with UDP on a Cyclone III and TSE and GigE link. I can't see not reaching 90Mbits+ on a 100MB interface. GigE makes a huge difference. 

--- Quote End ---  

 

 

--- Quote Start ---  

This is with a highly optimized driver, UDP packet generator and a hardware calculated TCP checksum. Without the hardware checksum but using an optimized assembly version I could exceed 500Mbits. 

--- Quote End ---  

 

 

Do you reach 900 MBits working only with the Nios Processor or do you implement a structure like in the UDP Offload example where you handle packages only in hardware?  

 

What kind of optimizations did you apply to the driver? Did you just place oftenly used functions to a tightly coupled memory like here:  

--- Quote Start ---  

placing key functions from newlib, µC OS and the TCP/IP stack in a tightly-coupled instruction memory. 

--- Quote End ---  

, or did you change the c code to work more efficiently?  

 

I would be very grateful for an answer and again I am sorry to pull out a thread that is 9 years old :/ 

 

cheers see
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