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Example design for Intel Arria 10 and Intel Cyclone 10 GX Avalon Streaming Interface for PCI Express

sgr
Beginner
616 Views

Hi,

  • Is there any example design available for Root port  of Intel Arria 10 and Intel Cyclone 10 GX Avalon Streaming Interface for PCI Express?
  • And one more question is what is the PIPE interface in this Block diagram? Is it only required for example design simulations?

Than you

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4 Replies
wchiah
Employee
595 Views

Hi,

 

Apologize for late reply.

  • If refer to latest release note of Arria 10 and Cyclone 10 for Quartus 20.4
  • https://www.intel.com/programmable/technical-pdfs/683487.pdf
  • You can enable the Root Port mode using the parameter editor.
  • The Root Port supports basic simulation and compilation.
  • However, the Root Port is not fully verified. You may find functional problems in the current release.

If referring to In Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express User Guide version 18.0

in table 11 for System Setting it is mentioned that Root Port mode only supports the Avalon-MM interface type.

https://www.intel.com/programmable/technical-pdfs/683647.pdf

If you need basic simulation and compilation, you may try to use it. For full function, you are advised to use the AVMM interface type.

 

For detail for pipe interface and how to implement it, you may refer official release demo video at the link below

https://www.youtube.com/watch?v=vprh7j0o8ks&ab_channel=IntelFPGA

 

Hope this answer your question, 

Regards,

Wincent_Intel

 

 


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Shifali15
New Contributor I
587 Views

Thank you for your input 

  • My doubts are still not solved because in table 3 it is clearly mentioned that Root Portis is supported for PCIe Hard IP for Avalon streaming interface.

cap_3.PNG

 

 

 

 

 

 

 

 

  • But in table 11 of the system setting it is mentioned that  Root Port mode only supports the Avalon-MM interface type.

cap_11.PNG

So, My question is whether PCIe Hard IP for Avalon streaming interface as Root Port mode is not supported in the example design or is it not supported as full function.

Please give your input as soon as possible.

 

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wchiah
Employee
558 Views

Hi,


Apologize for late reply. as previous reply the Rootport is supported but not fully verified.

You may refer to FPGA knowledge-based for known issue.

https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html#sort=%40articlepublisheddate%20descending


Regards,

Wincent_Intel



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wchiah
Employee
541 Views

Hi,

 

I strongly believe my previous reply answered your question. 

We do not receive any response from you to the previous answer that I provided.

This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


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