Exporting DSP Builder Modules to HDL Designs

[Altera_Forum]

Hi 

 We're considering purchasing the Quartus toolset for an upcoming project, in which we need to take logic created with DSP Builder and integrate it into a behavioral VHDL design, which would be simulated with Modelsim PE or SE.   Does DSP Builder or Quartus provide a mechanism for doing this? Essentially, there would be several Altera FPGAs instantiated in a testbench, and one or more of those FPGAs would contain blocks created with DSP Builder.   Each FPGA would have a VHDL top-level, with a mixture of behavioral VHDL and DSP Builder blocks. In other words, we don't want to simply generate a gate-level HDL model for each FPGA, and then instantiate those in a testbench, as this would make debugging more laborious. We want to be able to simulate our VHDL source.   Alternatively, is there a way to simulate a multi-FPGA design, containing a mix of VHDL source and DSP builder blocks, within DSP builder?   Thanks, Chris

[Altera_Forum]

try opening SignalCompiler and going to the Export tab, click Export, and select an output directory. 

 open the .qip to see what VHDL files are involved in the design and create your ModelSim script based on them. it may be a little trickier if you're using any MegaFunctions, you'll have to gather the .vho simulation model and any .hex/.mif used by the core.