F-Tile Auto-Negotiation and Link Training For Ethernet Intel FPGA IP registermap

[sunstar]

is there any more registermap info for "F-Tile Auto-Negotiation and Link Training For Ethernet Intel FPGA IP"? Especially for link training,there is only one reg can be read for status. It is diffcult to debug where is wrong for my situation.

[paveetirrasrie_Intel]

Hello Sunstar,

Please refer to https://www.intel.com/content/www/us/en/docs/programmable/683023/24-3/registers.html for more details about AN/LT registers and you may also download the Excel: https://cdrdv2.intel.com/v1/dl/getContent/637460 for AN/LT register map description.

Regards,

Pavee

[paveetirrasrie_Intel]

Hello,

I believe I've provided the necessary resources based on your query and we do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. 

If you have a new question, feel free to open a new thread to get the support from Altera experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.

Regards,

Pavee