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Altera_Forum

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07-24-2012
08:45 PM

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FFT Frequency Range

I am using the 50MHz internal clock of the Stratix III to collect samples of a chirp signal operating at 30kHz to 80kHz. I read in one of the forums that the FFT MegaCore output frequencies are 0~Fs/2 for samples 0~N/2-1, then -Fs/2~0 for samples N/2~N-1. With my 8192-point FFT, this would correspond to 0~25MHz for the first half of the samples. This means that my target range of 30-80kHz consists of only a few points. Is there any way to focus the FFT on only that range so I can get 1000+ points in the desired range? There is no clock input for the FFT MegaCore, so I cannot adjust the 50MHz clock (as far as I know). My goal is to view around1000 points of FFT data in this range using the SignalTap block. Any suggestions would be greatly appreciated.

Thanks, CoryLink Copied

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Altera_Forum

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07-25-2012
12:02 AM

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Altera_Forum

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07-25-2012
12:39 PM

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Altera_Forum

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07-25-2012
12:54 PM

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Unfortunately yes. You are in a situation when you have upsampled the signal

very high then you need to downsample back if you want that KHz of fft resolution. Try if you can apply lower sampling rate to your ADC level as it is way too high.
Altera_Forum

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07-25-2012
01:02 PM

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Thanks for the quick reply! I'll try sampling around 200kHz and see if that does the trick. By the way, if I want to look at the FFT results in SignalTap, how do I change the SignalTap clock to match the clock of the ADC and FFT? I can't seem to apply my PLL block to SignalTap since it doesn't appear as a choice in the Signal Compiler block under the SignalTap II tab. Since the slowest internal clock of the FPGA is 50MHz (which would be my base clock), how do you suggest I apply a slower clock to SignalTap?

Thanks again, Cory
Altera_Forum

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07-25-2012
01:11 PM

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Altera_Forum

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07-25-2012
01:19 PM

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Altera_Forum

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07-25-2012
01:32 PM

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Altera_Forum

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07-25-2012
01:42 PM

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Altera_Forum

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07-25-2012
02:21 PM

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Do you have any suggestions for obtaining a 500kHz clock since the PLL won't work?

Thanks, Cory
Altera_Forum

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07-25-2012
03:42 PM

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Altera_Forum

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07-25-2012
04:24 PM

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Ok, I think I have the ADC and FFT clocks working correctly, but I am still having issues syncing them with SignalTap. If I use a PLL block, SignalTap doesn't recognize it as an available clock. If I use a clock_derived block and use it for SignalTap, then SignalTap never stops collecting data; when I click "Acquire," SignalTap just freezes and I have to force quit Matlab. How do you suggest I slow down the SignalTap data acquisition so it is in sync with the FFT output data? Sorry to keep bugging you, but I feel like I'm getting close to making this thing work.

Thanks again, Cory
Altera_Forum

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07-25-2012
06:43 PM

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I don't quite get it but I will select fft clock to be the signaltap clock then select fft(input & outputs) to be data nodes and then acquire data (if necessary on some trigger condition).

You may need to select the category (all design entries) for signaltap selection.
Altera_Forum

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07-25-2012
07:53 PM

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Altera_Forum

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07-25-2012
08:09 PM

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You better delete your signaltap, delete dB and start fresh.

In your new signaltap select clock node by navigating to the fft clk node. Simialrly select data nodes as required. The clock need not be on a pin for signaltap. The timing issues have no effect on operation of signaltap tool itself. If you don't find these nodes set node finder to all design entries
Altera_Forum

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07-25-2012
08:23 PM

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Altera_Forum

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07-25-2012
08:42 PM

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Altera_Forum

Honored Contributor I

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07-25-2012
08:44 PM

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