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I am using the 50MHz internal clock of the Stratix III to collect samples of a chirp signal operating at 30kHz to 80kHz. I read in one of the forums that the FFT MegaCore output frequencies are 0~Fs/2 for samples 0~N/2-1, then -Fs/2~0 for samples N/2~N-1. With my 8192-point FFT, this would correspond to 0~25MHz for the first half of the samples. This means that my target range of 30-80kHz consists of only a few points. Is there any way to focus the FFT on only that range so I can get 1000+ points in the desired range? There is no clock input for the FFT MegaCore, so I cannot adjust the 50MHz clock (as far as I know). My goal is to view around1000 points of FFT data in this range using the SignalTap block. Any suggestions would be greatly appreciated.

Thanks, CoryLink Copied

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You haven't explained how is that you are using 50MHz clock to sample few KHz signal. Is it that your chirp is analogue and an ADC device is sampling at 50MHz ? or is your data digital in which case you cannot sample at such speed ?

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Kaz, the chirp is analog and I am sampling via the ADC at 50MHz. Does that mean I need to decrease the sampling rate in order to narrow the range of the FFT?

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Unfortunately yes. You are in a situation when you have upsampled the signal

very high then you need to downsample back if you want that KHz of fft resolution. Try if you can apply lower sampling rate to your ADC level as it is way too high.- Mark as New
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Thanks for the quick reply! I'll try sampling around 200kHz and see if that does the trick. By the way, if I want to look at the FFT results in SignalTap, how do I change the SignalTap clock to match the clock of the ADC and FFT? I can't seem to apply my PLL block to SignalTap since it doesn't appear as a choice in the Signal Compiler block under the SignalTap II tab. Since the slowest internal clock of the FPGA is 50MHz (which would be my base clock), how do you suggest I apply a slower clock to SignalTap?

Thanks again, Cory- Mark as New
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does that imply you will generate your ADC/fft clock from a PLL. I am not sure if PLL will support this low output. Whatever clock feeds fft/ADC you should be able to tap it to signaltap clock. Or you may add another copy of your clock and use it in signaltap.

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Thanks again, kaz! I will mess around a bit more with clocks and PLLs, and hopefully I'll get it working soon.

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Before you make changes you should know that with fft of 8192 resolution at speed of 50M you get each bin covering 6.104Khz i.e. about 8 bins will cover your signal (30~80KHz) on either side of dc. May be this enough

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Actually I would like several hundred bins. The signal compiler tells me that the slowest clock I can obtain with the PLL is 5MHz. Maybe I'll be able to get away with that.

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Do you have any suggestions for obtaining a 500kHz clock since the PLL won't work?

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Normally ADCs require clean clock signal for sampling but since you are dealing with KHz you may try generate clock from fpga logic (divide using counter) and apply it to both ADC and FFT. It will have jitter but your application may tolerate it.

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Ok, I think I have the ADC and FFT clocks working correctly, but I am still having issues syncing them with SignalTap. If I use a PLL block, SignalTap doesn't recognize it as an available clock. If I use a clock_derived block and use it for SignalTap, then SignalTap never stops collecting data; when I click "Acquire," SignalTap just freezes and I have to force quit Matlab. How do you suggest I slow down the SignalTap data acquisition so it is in sync with the FFT output data? Sorry to keep bugging you, but I feel like I'm getting close to making this thing work.

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I don't quite get it but I will select fft clock to be the signaltap clock then select fft(input & outputs) to be data nodes and then acquire data (if necessary on some trigger condition).

You may need to select the category (all design entries) for signaltap selection.- Mark as New
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Ok, I think my problem is solely with SignalTap. I use a PLL to slow the FFT clock, and I believe it is working fine. However, no matter what I do with the SignalTap clock, it still seems to sample and 50MHz. I tried using a clock_derived, but it just freezes during data acquisition. Could there be something wrong with my clock_derived pin assignment (or lack thereof)? Do I have to manually assign the clock_derived to a pin on the FPGA?

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You better delete your signaltap, delete dB and start fresh.

In your new signaltap select clock node by navigating to the fft clk node. Simialrly select data nodes as required. The clock need not be on a pin for signaltap. The timing issues have no effect on operation of signaltap tool itself. If you don't find these nodes set node finder to all design entries- Mark as New
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Thanks for bearing with me. What about in DSP Builder, where there isn't a node finder like in Quartus?

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I use dspbuilder to get code then move to quartus and build my project there. Can't you do that. I am not particularly keen to change platform away from Quartus.

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Ok, that's what I'll do. I was hoping to keep things relatively simple by using only DSP builder, but it just doesn't have as many options.

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