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FPGA Intellectual Property

Discussions

FFT v9.0

fir ii compiler 14.1 issue when decimating from <10MSPS

Internal memory usage using MegaWizard RAM: 2-port

enhanced precision troubles in DSP Builder 13.0.1

HDL Import [state machine in VHDL]

UART (RS232) IP without NIOS core

Qsys FIR filter did not work in testbench

How to implement DE0 SDRAM as 2-port RAM

fixed_point_fft

altera_onchip_flash

Arria V Starter Kit: SDI re-transmitter

Clocked Video Output to ALTLVDS_TX

After convolution of image at output not getting blurred image

FIR Compiler II fractional signed fractional binary (integer bits output width)

Subtraction of two images using block

Featured Content

Tone Mapping Operator IP Malfunctioning

dynamic configuration issue of fpll from arria 10

Unable to simulate DDR3 controller

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)