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Altera_Forum
Honored Contributor I
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UART (RS232) IP without NIOS core

I've been trying to test the behaviour of the UART IP using a test bench but I'm failing to get any output from txd. I've setup the following test bench but am not getting any results, can someone please tell me where I am going wrong? "readyfordata" never asserts and I'm not sure why. The address input relates to the last image (https://www.altera.com/en_us/pdfs/literature/ug/ug_embedded_ip.pdf). Please help! 

 

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY uart_vhd_tst IS END uart_vhd_tst; ARCHITECTURE uart_arch OF uart_vhd_tst IS -- constants -- signals SIGNAL clk : STD_LOGIC:='0'; SIGNAL ext_con_rxd : STD_LOGIC := '1'; SIGNAL ext_con_txd : STD_LOGIC := '1'; SIGNAL reset_n : STD_LOGIC := '0'; SIGNAL uart_address : STD_LOGIC_VECTOR(2 DOWNTO 0):="001"; SIGNAL uart_begintransfer : STD_LOGIC := '0'; SIGNAL uart_chipselect : STD_LOGIC := '1'; SIGNAL uart_dataavailable : STD_LOGIC := '0'; SIGNAL uart_read_n : STD_LOGIC := '1'; SIGNAL uart_readdata : STD_LOGIC_VECTOR(15 DOWNTO 0):=(others=>'0'); SIGNAL uart_readyfordata : STD_LOGIC:='0'; SIGNAL uart_write_n : STD_LOGIC := '1'; SIGNAL uart_writedata : STD_LOGIC_VECTOR(15 DOWNTO 0):=(others=>'0'); COMPONENT uart PORT ( clk : IN STD_LOGIC; ext_con_rxd : IN STD_LOGIC; ext_con_txd : OUT STD_LOGIC; reset_n : IN STD_LOGIC; uart_address : IN STD_LOGIC_VECTOR(2 DOWNTO 0); uart_begintransfer : IN STD_LOGIC; uart_chipselect : IN STD_LOGIC; uart_dataavailable : OUT STD_LOGIC; uart_read_n : IN STD_LOGIC; uart_readdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); uart_readyfordata : OUT STD_LOGIC; uart_write_n : IN STD_LOGIC; uart_writedata : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; BEGIN clk <= not clk after 20 ns; i1 : uart PORT MAP ( -- list connections between master ports and signals clk => clk, ext_con_rxd => ext_con_rxd, ext_con_txd => ext_con_txd, reset_n => reset_n, uart_address => uart_address, uart_begintransfer => uart_begintransfer, uart_chipselect => uart_chipselect, uart_dataavailable => uart_dataavailable, uart_read_n => uart_read_n, uart_readdata => uart_readdata, uart_readyfordata => uart_readyfordata, uart_write_n => uart_write_n, uart_writedata => uart_writedata ); init : PROCESS -- variable declarations BEGIN reset_n <= '1' after 100 ns; WAIT; END PROCESS init; always : PROCESS -- optional sensitivity list -- ( ) -- variable declarations BEGIN -- code executes for every event on sensitivity list uart_writedata <= x"00F0" after 100 ns; uart_write_n <= '0' after 140 ns; uart_begintransfer <= '1' after 140 ns; WAIT; END PROCESS always; END uart_arch; 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10444&stc=1  

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10445&stc=1
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