FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
All support for Intel NUC 7 - 13 systems has transitioned to ASUS. Read latest update.
6312 Discussions

fir ii compiler 14.1 issue when decimating from <10MSPS

Honored Contributor II

So I'm working on a system with 3 decimation filters starting from 20msps and going down to 2.5msps.  

The first 2 filters display a respone similar to the MATLAB results but the 3rd one shows a response at 1khz filter instead of 1mhz, the issue occurs when I set the sample rate to less than 10msps.  


Is there anything I can do?
0 Kudos
1 Reply
Honored Contributor II

A couple of updates if anyone is intrested: 

1. the problem occurs only when the output sample rate reaches below 5msps, meaning that decimaiton and single rate under said sample rate will cause this bug. 

2.I don't think the bug is passed on to the design and only a visual bug with the IP compiler, I will know if that is the case soon. (comparing results with my matlab simulation)
0 Kudos