FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5917 Discussions

FIFO megafunction usedw signal not working

thadoe
Novice
212 Views

Hello everyone,

 

I am trying to use Altera dual clock FIFO on Cyclone IV E . Both wrusedw and rdusedw not updating (staying at zeros)

 

I want to use MSB bit of usedw to get a half full flag for read logic.

wrclk is 3.2MHz

rdclk is 100MHz

depth is 2k words

data width is 16 bit

 

I checked lpm_widthu, which is correctly set to 11. Both underflow and overflow checking are enabled.

Where am I doing wrong. Any help would be much appreciated.

0 Kudos
1 Solution
SyafieqS
Moderator
138 Views

Hi Thadoe,


Is this signal identified during signaltap or simulation? Assuming you are tapping it, you might need to verify simulation for the signal before hardware implementation, make sure the behavior is correct.


View solution in original post

1 Reply
SyafieqS
Moderator
139 Views

Hi Thadoe,


Is this signal identified during signaltap or simulation? Assuming you are tapping it, you might need to verify simulation for the signal before hardware implementation, make sure the behavior is correct.


Reply