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Hello everyone,
I am trying to use Altera dual clock FIFO on Cyclone IV E . Both wrusedw and rdusedw not updating (staying at zeros)
I want to use MSB bit of usedw to get a half full flag for read logic.
wrclk is 3.2MHz
rdclk is 100MHz
depth is 2k words
data width is 16 bit
I checked lpm_widthu, which is correctly set to 11. Both underflow and overflow checking are enabled.
Where am I doing wrong. Any help would be much appreciated.
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Hi Thadoe,
Is this signal identified during signaltap or simulation? Assuming you are tapping it, you might need to verify simulation for the signal before hardware implementation, make sure the behavior is correct.
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Hi Thadoe,
Is this signal identified during signaltap or simulation? Assuming you are tapping it, you might need to verify simulation for the signal before hardware implementation, make sure the behavior is correct.
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