FIR filter design in VHDL

[Altera_Forum]

Hi All, 

 I am new to DSP/FIR filter design. I have a few basic questions in regards to the FIR filter design in VHDL.    I have to design    1.FIR High Pass Filter at 300 Hz (basically to remove 30 Hz and to pass 1020 Hz). 2.FIR Low Pass Filter at 100 Hz (to pass 30 Hz).   My Cyclone 3 FPGA currently occupies 75 % of resources and have only 10 multipliers left. Because of this , I decided to go with the Time Multiplexed architecture design. Hence I am storing the unfiltered input data into RAM and this goes to the MAC (Multiply and Accumulate ) unit which also gets a 16-bit coefficient data from the Coefficient ROM. Now I am planning to use the Altera Embedded BlockRAM memories to do this. But now the question is how am I going to know the depth of the RAM? which in turn means I need to calculate the number of taps required for both these filters.     My input data is 16 bit wide and output is also 16-bit wide. Can someone give me ideas on this?   Many thanks in advance BPR

[Altera_Forum]

Do you mean "How much memory is left in your device". This should be clear in your compiler report. 

 Your LPF cutting off at 30 (Fs of 100) is pretty basic, 15 taps may enough. Your HPF cutting off at 30 (Fs of 300) may require 21 taps(also notice 1020Hz is wrong, possibly typo).   Since you have few multipliers but slow circuit, I suggest using one MAC running at 21 times data(HPF) or 15 times data(LPF).   You need to store upto 21 stages of input/data and ceffs. So it is not a problem.

[Altera_Forum]

--- Quote Start ---  1020Hz is wrong, possibly typo  --- Quote End ---  I guess, 100/300 Hz are meant as cutoff frequencies. Sample frequency isn't mentioned at all.

[Altera_Forum]

Hi Kaz & FvM, 

 Thank you for your explanations/query.   Yes FvM 100/300 Hz are the cutoff frequencies. The sample frequency is 792 kHz.    Kaz, can you please elaborate on how you came up with the tap numbers of 15 & 21 from the sampling and cut off frequencies. And don't worry about 1020 Hz.    In regards to memory/block ram what I was refering to was , since I am storing the filter input data and the coefficient data in RAM & ROM respectively, I need to know the number of filter taps to know the RAM/ROM depth. Hope that makes sense.   BPR

[Altera_Forum]

Hi, 

 I used Matlab fir1 and checked the filter: e.g. for a HPF with cutoff of 30(Fs = 300) then I entered:   h=fir1(20,2*30/300, 'H'); freqz(h)   Note: Matlab assumes Nyquist = 1(i.e. half Fs = 1) for its functions and display and this is at times really irritating as everybody things of Fs = 1.   On the graph of freqz you can measure transition band and dB at various points. Normally your spec decides what dB should be achieved at certain frequencies.   Now I take it that your paired values represent the edges of transition band. if your Fs = 792KHz then you are in trouble, you will need a large number of taps.    You may apply decimation to come down on Fs possibly in a cascade but you will need to filter off anything more than targeted Nyquist(1/2 Fs) then decimate. This approach best helps if your signal is already filtered and does not have high freq energy.

[Altera_Forum]

--- Quote Start ---  You may apply decimation to come down on Fs possibly in a cascade but you will need to filter off anything more than targeted Nyquist(1/2 Fs) then decimate.   --- Quote End ---   CIC decimation filters provide sufficient filtering of alias frequencies for many applications.

[Altera_Forum]

Yes indeed CIC is best for high changes of sampling rates. The problem is their sinc distortion. This mostly will need inverse sinc compensation filter(before/after filter or incorporated in the coeffs of required filter).