GTS PMA/FEC Direct Transceiver Streaming

[K606]

I have been trying to set up the GTS PMA/FEC Direct on the Agilex 5 and would like to know how to stream parallel data to/from the GTS when the GTS does not expose a AV-Sink/Source on the parallel data interfaces?

A pic of the IP for reference:

Thanks!

[K606]

Hi - I cannot see this image!

[CheePin_C_Intel]

Hi,

Sorry about the image display issue. I am trying to refer the following section "6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design" as in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs user guide. I extract some of the texts from the user guide as following. You may double check on the commenting out specific 2 lines in the .qsf file.

"You can perform hardware testing of the example design on the Agilex 5 FPGA ESeries

065B Premium Development Kit (ES1) board. You must select this

development kit in the Select Board setting in the Example Design tab of the IP

GUI, so that the reference clock and channel pin assignments are generated for the

development kit’s hardware design by the Quartus Prime software in the .qsf file.

If you require to change the pin assignments of the example design, you can comment

the following lines in the example_design.qsf file.

#set_global_assignment -name POST_MODULE_SCRIPT_FILE

"quartus_sh:board_assignments.tcl"

#set_global_assignment -name PRE_FLOW_SCRIPT_FILE

"quartus_sh:board_assignments.tcl"

After you have commented out the lines, you can set the pin assignments according to

your board setup and the assignments are reflected in the example design."

Please let me know if the issue still persists after you tested the above.Thank you.

[K606]

Ah yes - I followed this already

[CheePin_C_Intel]

Hi,

Thank you for the update. From what I understand, you've commented out the two lines in the .qsf file before proceeding with your own assignments based on the Terasic devkit. However, you still observe issue when running the loopback tests using the TCL script. Given the complexity of the current setup, it might be helpful to take a step back and explore a simpler design or configuration to isolate the issue more effectively. As you may know, the GTS PHY example design was validated using the Altera devkit.

Since this thread originally focused on data streaming, and our latest discussion is branching into different area, would you mind opening a new thread for this topic on bring up the GTS design in Terasic devkit? This will help us keep the discussions organized and make future reference easier. Once you've created the new thread, please share the link with me so we can continue the investigation there.

In the meantime, you might consider the following steps:

1. Check XCVR Routing: Confirm whether your Terasic devkit has XCVR channels routed to the FMC+ connectors.

2. Start with a Known Example: If yes, try using the "1 x 1G PMA Direct Mode (System PLL Clocking) with Custom Cadence" example design. Assign the pins ie resets, clock, XCVR and etc accordingly and perform an external loopback using the FMC+ loopback card.

3. Fixed data pattern: You can send fixed data pattern to the TX ie 0xBC... to ease the debugging and monitoring at the RX parallel output after external loopback.

4. Add SignalTap: Include SignalTap in your design to monitor key status signals such as GTS resets, ready, pll_locked, CDR lock status, freq_valid, etc. Refer to Figure 88 in the GTS User Guide for guidance on which signals to observe.

5. Run and Capture: Deploy the design on the Terasic devkit and capture the SignalTap results.

6. Compare and Debug: Compare the captured signals with the original simulation results from the example design. If you notice any anomalies, feel free to share the SignalTap capture for further analysis.

Looking forward to your findings in the new thread. Let me know if you have any concerns or need assistance setting it up.

[CheePin_C_Intel]

Hi,

I believe that your initial question of this thread has been addressed, I now transition this thread to community support. Feel free to open a new thread on bring up the GTS design in Terasic devkit as discussed previously.