GTS Transceiver PHY - Reference Clock Network

[K606]

I am trying to understand the GTS Clocking Network.

In the user guide doc here, it is possible to see the following suggested design:

However later in the doc, we can see this statement:

Which is a confusing suggestion, as it suggests an the input clock to the SysPLL should control the i_rx_cdr and i_tx_pll.

Is there somewhere else that explicitly explains how to connect these three regional/local-ref clocks? Are they all connected to the same reference clock?

Many Thanks!

[CheePin_C_Intel]

Hi K606,

Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible.

[CheePin_C_Intel · Accepted solution]

Hi,

Apologies for the delayed response.

As I understand it, you have some questions regarding the connections for i_rx_cdr and i_tx_pll of the PHY, as well as i_refclk for the system PLL. For your reference, in the example design, all three reference clocks are configured to operate at the same frequency. Therefore, it is recommended to connect them to the same clock source.

Please let me know if you have any concerns or need further clarification. Thank you!

[CheePin_C_Intel]

Hi,

I believe that your initial question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you very much.