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Hello,
I implemented the Generic Serial Flash Interface to connect to a W25Q80DVSSIG TR 8Mb serial flash. I would like to use simple SPI: so I have CLK, nCS, MISO and MOSI to connect.
The HDL generated shows:
board_flash_spi_qspi_pins_dclk : out std_logic;
board_flash_spi_qspi_pins_ncs : out std_logic;
board_flash_spi_qspi_pins_data : inout std_logic_vector(3 downto 0) := (others => 'X');
Data is an "inout" type of 4 bits, which looks ok for Quad SPI. However I only have MISO and MOSI.
How to connect this? There's no explanations in the IP documentation.
How to set the interface mode (Quad, dual, single)? There's no option in the Platform Designer.
PS additional notes:
I'm using a MAX10 10M08SAU device, with Quartus 18.1, and I'm using VHDL language.
Thanks and best regards,
Giaime
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No one to step in?
Thanks in advance and best regards
Giaime
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Hi Giaime Ugliano,
Sorry for the late. The IP supports Single, Dual and Quad mode. No setting is needed on the IP for Single, Dual and Quad mode. It is on the flash. If your flash support single, dual and quad mode, you will need to enable it on flash using Generic Serial Flash IP.
I just checked the flash datasheet, seems like it has 4 data I/O pin as well. You can just connect the 4 data I/O pin with the QSPI_PINS_Data.
Thank You
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Hello Bruce,
thank you very much for your reply!
The issue is, the PCB is already done connecting only MISO and MOSI to the FPGA. This is because the Flash itself defaults to single SPI mode, if you don't use the special instructions.
In this case, how do you think it's best to connect the pins? They're INOUT type, while my MISO is IN and MOSI is OUT types. How to handle that?
Thank you very much in advance,
best regards
Giaime
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Hello,
I have a customer with the same question. The SPI flash W25Q01JV is a 1Gbit flash with single DI and DO.
The Generic Serial Flash IP user guide says it supports single, dual and quad SPI flash, but there is no selection in the IP wizard to set this. The Generic Serial Flash IP appears to support only quad-SPI. How does the user configure this IP for single-SPI?
Thank you.
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I also have the same question. The Generic Serial Flash Interface Intel FPGA IP simply shows a 4-bit QSPI data line. There is no instruction in the user guide (https://www.intel.com/content/www/us/en/docs/programmable/683419/24-1-20-2-5/user-guide.html) for how to set up single mode! Are we supposed to guess and check where the MOSI & MISO lines go?
Come on Intel/Altera! 5 years since the original post and still no answer?? Disappointing.
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Hi,
the answer is in any QSPI flash datasheet of your choice. Flash SPI access always starts in single mode, therefore they have a fixed mapping of MOSI (flash DI) and MISO (flash DI) to IO[3:0] lines. You'd know if you read any. DI is IO0, DO IO1. The assignment should be fixed in a JEDEC standard, I didn't check because it's obvious for me.
Anyway I agree that the question could have been answered clearly from the start.
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Thank you!!
The answer is indeed in the flash datasheet of my device. Its my first time working through this scenario and I was baffled by the vagueness of the IP user guide.

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