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Generic Serial Flash Interface reading only 0's

Jcole
New Contributor I
1,767 Views

Hi, I'm using the Cyclone 10 EVAL kit with the EP128A flash connected. I perform the following events and made sure that the csr /mem wait requests were low before issuing the next command, but only get all 0x00 for read responses (Signal Tap screenshots are attached):

WR ENABLE:
csr_addr: 0x07  csr_wr_data: 0x00000006
csr_addr: 0x08  csr_wr_data: 0x00000001

SECTOR 0 ERASE:
csr_addr: 0x07  csr_wr_data: 0x000003D8
csr_addr: 0x09  csr_wr_data: 0x00000000

csr_addr: 0x08  csr_wr_data: 0x00000001

 

WR 4 BYTES OF DATA TO ADDR 0x4000:
csr_addr: 0x04  csr_wr_data: 0x00000000
csr_addr: 0x00  csr_wr_data: 0x00000001

csr_addr: 0x06  csr_wr_data: 0x00000502

mem_addr:0x4000 mem_wr_data: 0x0011223

mem_addr:0x4000 mem_wr_data: 0x44556677

mem_addr:0x4000 mem_wr_data: 0x8899AABB

mem_addr:0x4000 mem_wr_data: 0xCCDDEEFF

 

READ DATA BACK:

csr_addr: 0x04  csr_wr_data: 0x00000000
csr_addr: 0x00  csr_wr_data: 0x00000001
csr_addr: 0x05  csr_wr_data: 0x00000001

mem_addr:0x4000

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Jcole
New Contributor I
1,643 Views

So it seems the issue has been with Signal tap all along, when I changed my trigger conditions to make sure pivotal actions were hit, then set my Storage enables to output when the rising edge of "avl_mem_readdatavalid", I was able to see valid and correct read data from the Flash.

View solution in original post

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5 Replies
FvM
Honored Contributor II
1,746 Views

Looks better than your previous tries. Something is probably still missing . I'm not yet using General SFI IP, prefer simple and straightforward ASMI instead. I see that a lot of parameters has to be set.

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Jcole
New Contributor I
1,722 Views

This one is supposed to use the active serial, is there something I need to set before hand that I possibly overlooked?

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Jcole
New Contributor I
1,692 Views

I added an additional Write Enable and Sector Unprotect command before the WR 4 BYTES OF DATA TO ADDR 0x4000, but still only reading back 0's. Added commands are below:


WR ENABLE:
csr_addr: 0x07  csr_wr_data: 0x00000006
csr_addr: 0x08  csr_wr_data: 0x00000001

SECTOR 0 UNPROTECT:
csr_addr: 0x07  csr_wr_data: 0x00001001
csr_addr: 0x0A  csr_wr_data: 0x00000000

csr_addr: 0x08  csr_wr_data: 0x00000001

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Jcole
New Contributor I
1,644 Views

So it seems the issue has been with Signal tap all along, when I changed my trigger conditions to make sure pivotal actions were hit, then set my Storage enables to output when the rising edge of "avl_mem_readdatavalid", I was able to see valid and correct read data from the Flash.

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JingyangTeh
Employee
1,525 Views

Hi


Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome to reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Regards

Jingyang, Teh


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