Getting Started with Cyclone V PCIe Streaming

[Alexander_M_Intel]

Hello, I am trying to learn how to read data from an FPGA through a PCIe link. I'll put all of the specifics to my setup at the bottom of this post. 

Right now, I am trying to just learn how to stream some data from the FPGA to the desktop (through the PCIe link).

Long term, I want to be able to stream data in, process it, stream data out.

I successfully programmed my Cyclone V GT Development Board with this reference design (gen 1, 1 lane): https://www.altera.com/content/dam/altera-www/global/en_US/others/support/refdesigns/ip/interface/PCIe_CVGT_AVST_On_Chip_Mem_150.zip

I tried to slightly modify the design by replacing the input to the DUT (the hard IP) component's avalon streaming sink with a component that streams some random, known data. The design compiles and writes to the FPGA properly, but I don't know what to do to check if and where the data is being written to on the host PC.

I am also using CvP Initialization and Update Mode to program it (if that's relevant). The driver I use to program it has no functionality outside programming the board. 

If someone could inform me if I am on the right track or point to a simple example, I would greatly appreciate it.

Board: Cyclone V GT Development Kit

Distribution: Ubuntu 16.04

Quartus Prime Version: 18.0

Best Regards, Alex

[Alexander_M_Intel]

Hello, I am still trying to learn about how to stream data through PCIe. While I have learned more about the topic, I have some questions that I hope someone can answer.

So my main short term goal is to take some data originates in the FPGA and actually get it into my desktop in a place that I can read it. Ideally, I would avoid overhead as much as possible and get the simplest starting design to work from, but I will take what I can get for the time being.

Here are my questions:

1.) Is my understanding of what the PCIe HIP does correct?

In the PCIe HIP for Avalon Streaming there are a multitude of BARs that can be configured in Platform Designer. My understanding of how these work is that when the BIOS for the desktop is starting up, it sees this information and assigns a memory address range accordingly. All reads and writes to this address should actually initiate some PCIe interaction and the "physical" or literal memory that is associated with these addresses is on the PCIe device itself, i.e. the FPGA.

Is what the HIP does is handle the initial PCIe setup and all other PCIe protocol nonsense, minus creating the PCIe credits? Should it basically take in or spit out avalon streaming data, output some debug/status info and take credits in from the user application?

2.) So I know the desktop can initiate reads when some user application requests it (assuming all necessary drivers / kernel magic is set up correctly), but is it possible for the FPGA to just write to somewhere in the desktop's memory? If this is possible is it something that I should consider or does it have unintended harmful consequences?

3.) I've read through large parts of the documentation on the high performance reference design, but I don't understand exactly how I can go about creating my own user application to replace the example Chaining DMA Application. I've tried to look at the actual HDL code that is auto generated from the IP catalog, but the dozens of verilog and system verilog files are less than readable.

Could someone provide some advice about where I could start? In Platform Designer the clocks and rx/tx signals seem like they should be simple enough, but I don't know what to do for the PCIe credits (signal tx_cred) and I still haven't memorized what the other half dozen acronyms even stand for. Which of these signals are even required for the HIP core to function properly?

4.) I have some high level understanding of how PCIe works, but the protocol is quite complex, so I would like to know how much I need to learn to get my design functioning. So, I need to handle generating PCIe credits in order to receive data properly, correct? In essence, I generate credits to inform the desktop what buffer memory is available or not available in the FPGA.

Is this actually as simple as having a counter increment when I "clear" data from whatever memory and decrementing every time I receive application data from the desktop? I still don't understand how much of this I actually need to implement or how much is already implemented in the HIP core itself.

I know I asked a lot of questions, I appreciate anything that you can do to help.

Best Regards, Alex