[HDMI IP] Auxiliary Packet Encoder -> Data Width -> could be changed?

[amildm]

Hi All,

Is it possible to change a width of the aux_data width in the HDMI IP? By default it's defined to be 72bit. 

This input port belongs to the Auxiliary Packet Encoder Data of the HDMI IP. 

Thanks!

[ZH_Intel]

Hi Amildm,

Good day.

Thank you for reaching out.

Apologize for the delayed response as we encounter some technical difficulty.

Regarding to your question, our internal team informed that Intel HDMI IP has the fixed format. You can re-wrap it to another format. 

Hope this answers your question.

Thank you.

Best Regards,

ZH_Intel

[amildm]

What do you mean "re-wrap it to another format"? Could you please provide an example? 

[ZH_Intel · Accepted solution]

Hi Amildm,

Good day.

Thank you for your patience.

Regarding to your question, you can wrap it based on your equipment, and Intel can only provide the aux-data format.

The aux-data width is not changable but you can wrap it to another format.

Customer can re-organize it to another format which means re-organize the structure/positioning of data.

HDMI Intel® FPGA IP User Guide

Intel provide the aux_data interface to show HB0~HB2, PB0~PB27....

There are only 4 phases for aux_data interface. on the 1st phase, aux_data[71:0] presents {PB22,PB21,PB15,PB14,PB8,PB7,PB1,PB0,HB0} and so on

You may re-organize it based on the same phase/block.

You can store all HB/PB registers in 4 phases into 72 registers. then re-organize them to another structure.

Hope this answers your question.

Thank you.

Best Regards,

ZH_Intel

[ZH_Intel]

Hi Amildm,

Thank you for your respond.

With your respond to accepted solution, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. 

Thank you.

Best Regards,

ZH_Intel