HDMI IP Example Design On Arria 10 SoC Development Kit

[YBilg]

Hello,

I am working on HDMI IP with Arria 10 SoC Development Kit. I have impelented the example design with the help of HDMI IP Example Design User Guide in Quartus 18.1. When I run the FPGA and Nios codes from the example design I can receive the video which is streaming from an external HDMI source and the video format is 1920x1080p 60fps. I can observe the TMDS signals in signaltap. The TMDS clock is 148.35 Mhz which is correct and can also be observed by an osciloscope on the daughter card. But when it comes to TX part of the example design, I can't even boot up the IP so there is nothing on the monitor that I'm using for TX part. The HDMI TX IP only streams constant numbers from r,g,b signals.  The constant numbers are the same for these three channels and it's D5354h. Since the data rate is below 3.4 Gbps for 1080p video standard, the TMDS_bit_clock_ratio and Scrambler_Enable signals are driven low.  Also, since the data rate is above minimum data rate ls_clk signal is connected to tx_clk which is output clock of the transceiver pll.

How can I solve this problem? Can somebody help me please, I'm stuck. 

[Deshi_Intel]

Hi,

May I know are you using exact HDMI Rx to Tx retransmit example design or your own modified HDMI design ?

The original A10 HDMI Rx to Tx retransmit example design is meant for A10 GX dev kit board, not A10 SOC dev kit board. So, I am not sure whether all the pin mapping is done correctly on A10 SOC dev kit board or not.

If possible, pls try out on A10 GX dev kit board to validate your hardware setup first.

Thanks.

Regards,

dlim

[YBilg]

Hi @Deshi_Intel  ,

I know that the A10 HDMI Rx to Tx retransmit example design is meant for A10 GX dev kit board, but it can be generated for other boards too. So, we did the pin mapping and esc. very carefully.

Since we completed the RX part successfully but we couldn't be able to success on the TX part; we have generated our own TX design and removed the RX and Nios parts. We just tried to display the test pattern which is generated by the test pattern generator in the simulation files. But we couldn't boot up the IP neither in FPGA nor in simulation. After 14 clocks of the resetting situation of the HDMI_TX IP, it just generates the constant values that I have described above. Unless we set the Scrambler_enable signal to high, it does not generates any outputs.

Regards,

Yıldız

[Deshi_Intel]

Hi Yıldız,

One question - Does HDMI tx failed on certain video resolution only or complete failure across all video resolution ?

1. May I know which Quartus version that you used ? Have you tried out latest Quartus version ?
2. Are you using Quartus in Linux OS or Win OS ?

My concern is whether the HDMI example design is generated correctly or corrupted.

• Do you still have the HDMI example design generation log file ? Can you review the log file for potential warning message ?
• Have you validated the software folder in HDMI example design ? Is it generated correctly as this is the main software design that control HDMI Tx ?

Thanks.

Regards,

dlim

[YBilg]

Hi @Deshi_Intel ,

I am using Quartus 18.1 in Windows. We are going to use Quartus 19 as soon as we get the license. 

Our HDMI source generates 1080p video, so we just tried for this resolution. Since the HDMI source and monitor support HDMI 1.4, on the TX part there is no need for SCDC communication. Also, we didnt enable scrambling because on HDMI 1.4. there is no scrambling. We have simulated the HDMI IP in Quartus 15 and Quartus 18.1 in this configuration. In Quartus 15, HDMI IP(version 15) generates r,g,b,c; but does not generate in Quartus 18.1. Firstly, we want to boot the IP in simulation, after that we will continue in hardware.

Regards,

Yıldız

[Deshi_Intel]

HI,

FYI... since you already had hardware board then you can straight ahead to try out the Quartus design on hardware testing instead of relying on simulation.

Earlier you mentioned HDMI Rx is working while failure only happened on HDMI Tx.

• Then the question will be whether the failure occurs in Rx to Tx transmission path or on the HDMI Tx IP itself
• I saw you mentioned you modified HDMI IP a lot. Perhaps you can stick with original IP design first to see whether it works before you work on your modification. Just worry the design modification accidentally break the HDMI IP functionality.
• Also, I found below HDMI Tx only design. You can try it out and cross check with your design also.
• https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/hdmi-tx-only-vip-suite-design-for-arria-10/

Ideally the recommendation is to stay with Intel FPGA HDMI example design "untouched with exception on pin mapping changes", get it working first before you start modify the design.

Thanks.

Regards,

dlim

[YBilg · Accepted solution]

Hi @Deshi_Intel  ,

We have finally solved the problem by supporting auxiliary in qsys user interface of HDMI IP and generating the .sof file again. 

Thank you for your support.

Regards,

Yıldız

[Deshi_Intel]

Hi Yıldız,

Good news indeed !

Alright, wish you all the best in your project development.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim