HPC II/ALTMEMPHY: How to write DDR3 mode registers

[Altera_Forum]

In table 1-3 "DDR3 SDRAM HPC and HPC II Features" on page 1-4 of the "DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide", it states that the HPC II will allow the user to perform "Optional run-time configuration of size and mode register settings, and memory timing". I am using an HPC II/ALTMEMPHY combination, and would like to write the DDR3 Mode Registers during run time for testing purposes. I can find no documentation on how to do this, and looking at the example driver and HPC II interface shows no obvious way of doing this. 

 I am using a Stratix IV device.   How do I write the DDR3 mode registers during run time with values that I provide that may be different from the values used when the HPC II was created with MegaWizard?   Thanks. 

[Altera_Forum]

When enabled it creates a standard Avalon interface for reading and writing to the register space. Register space is listed in the handbook starting at table 7-9.

[Altera_Forum]

Thanks for your post, std_logic. 

 I am aware the table that you reference, and before posting I verified that I could cause a recalibration cycle by writing bit 2 of the register at address 0x100 on then off. However, I have not been able to change the values that are written out to the RDIMMs (as far as I can tell). I am assuming that the values I want to write to the RDIMM Mode Registers need to be written to the registers at addresses 0x005 and 0x006. However, writes (and reads) to those addresses appear to have no effect. Is there something wrong with my assumption or my procedure?   Thanks!

[Altera_Forum]

I dont believe the RDIMM mode registers can be updated. If its not in the documentation then I doubt you can do it.