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I've been trying to run the runtb.do script created when instantiating a PCIe hard block with the MegaWizard. It always fails with incorrect number of ports in the generated modules. Has anyone successfully simulated this config?
I've tried PCIe gen1 x1, and a PCIe gen2 x8, and they both fail the same way. Tools are QII 9.1sp1 and ModelSim-AE 6.5b. I would expect the instance to run without issue; nothing was touched. Did Altera maybe update the core or testbench, but not both?? Here's the ModelSim transcript output:# Loading work.altpcierd_cdma_ast_rx_64# ** Warning: (vsim-3017) ../../common/testbench/altpcietb_bfm_rpvar_64b_x8_gen1_pipen1b.vo(68096): - Too few port connections. Expected 37, found 36.# Region: /pci_test_chaining_testbench/rp/rp/niilO0i# ** Warning: (vsim-3722) ../../common/testbench/altpcietb_bfm_rpvar_64b_x8_gen1_pipen1b.vo(68096): - Missing connection for port 'fbmimicbidir'.# ** Warning: (vsim-3017) ./pci_test_chaining_testbench.v(585): - Too few port connections. Expected 31, found 30.# Region: /pci_test_chaining_testbench/ep# ** Warning: (vsim-3722) ./pci_test_chaining_testbench.v(585): - Missing connection for port 'tx_st_err0'.# ** Warning: (vsim-3017) ../pci_test_example_chaining_pipen1b.v(453): - Too few port connections. Expected 100, found 89.# Region: /pci_test_chaining_testbench/ep/epmap# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'derr_cor_ext_rcv0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'derr_cor_ext_rpl'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'derr_rpl'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'ko_cpl_spc_vc0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'npd_alloc_1cred_vc0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'npd_cred_vio_vc0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'nph_alloc_1cred_vc0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'nph_cred_vio_vc0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'r2c_err0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'reset_status'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(453): - Missing connection for port 'suc_spd_neg'.# ** Warning: (vsim-3017) ../../../pci_test.v(494): - Too few port connections. Expected 39, found 36.# Region: /pci_test_chaining_testbench/ep/epmap/serdes# ** Warning: (vsim-3722) ../../../pci_test.v(494): - Missing connection for port 'rx_patterndetect'.# ** Warning: (vsim-3722) ../../../pci_test.v(494): - Missing connection for port 'rx_syncstatus'.# ** Warning: (vsim-3722) ../../../pci_test.v(494): - Missing connection for port 'tx_clkout'.# ** Warning: (vsim-3017) ../../../pci_test.v(639): - Too few port connections. Expected 152, found 140.# Region: /pci_test_chaining_testbench/ep/epmap/wrapper# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'avs_pcie_reconfig_readdata'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'avs_pcie_reconfig_readdatavalid'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'avs_pcie_reconfig_waitrequest'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'dprioreset'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'ev_128ns'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'ev_1us'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'int_status'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'serr_out'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'swdn_wake'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'swup_hotrst'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'use_pcie_reconfig'.# ** Warning: (vsim-3722) ../../../pci_test.v(639): - Missing connection for port 'wake_oen'.# ** Error: (vsim-3389) ../../../pci_test_core.vo(2509): Port 'extraclkout' not found in the connected module (83rd connection).# Region: /pci_test_chaining_testbench/ep/epmap/wrapper/n0l1ii# ** Error: (vsim-3389) ../../../pci_test_core.vo(2509): Port 'r2cerr0ext' not found in the connected module (114th connection).# Region: /pci_test_chaining_testbench/ep/epmap/wrapper/n0l1ii# ** Error: (vsim-3389) ../../../pci_test_core.vo(2509): Port 'successspeednegoint' not found in the connected module (159th connection).# Region: /pci_test_chaining_testbench/ep/epmap/wrapper/n0l1ii# ** Fatal: (vsim-3365) ../../../pci_test_core.vo(2509): Too many port connections. Expected 219, found 222.# Time: 0 ps Iteration: 0 Instance: /pci_test_chaining_testbench/ep/epmap/wrapper/n0l1ii File: C:/tools/altera/91/modelsim_ase/win32aloem/../altera/verilog/src/stratixiv_pcie_hip_atoms.v# FATAL ERROR while loading design# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./runtb.do PAUSED at line 97
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Have you installed the service pack for Modelsim 6.5b for Quartus II 9.1 that is shown on Altera's website? I seem to remember running into a similar port mismatch issue that was resolved when I installed the service pack for modelsim.
I can't say for sure that this is the exact issue, but it smells very similar to what I ran into...- Mark as New
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Do you know where this patch is? The page at https://www.altera.com/support/software/download/eda_software/modelsim/msm-index.jsp only shows 6.5b as the latest ... It would be awesome if a patch solved my issues!
Peter- Mark as New
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Peter,
Here is how I found the patch: (1) go to altera.com (2) hover over "Products" and select "Design Software" from the dropdown (3) click on the "Quartus II Subscription Edition Software" link (4) click on the "Download Software" link under "Next Steps" (5) select the "Download Service Pack" link under the "Download" button for Modelsim-Altera Starter Edition v6.5b for Quartus II v9.1 I hope this helps.- Mark as New
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That fixed it! Thanks for the pointer!
It's weird that my ModelSim is still 6.5b - I guess there's no indication of which service pack is being used. Peter- Mark as New
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Peter,
Glad that it fixed it...I agree, it would be nice if there was an indicator stating that the service pack was installed or not. Actually, now that I think about it, the update is probably a library update, not an update to the modelsim code...- Mark as New
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Ya that would make more sense. It's a big update though - 600 MB. I was thrown off by the fact that the ports really are mismatched in the RTL, making me think Altera was generating the wrong code. Anyways I'm glad I can do sims now!
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