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NShah22
Beginner
205 Views

Hello, there is no link for cyclone V native transceiver reference design for 16 bit data transfer using 8b/10b encoding. can u provide the link please!!!

on cyclone V transceiver files page, there is description of this design but no link for file download.

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8 Replies
CheePin_C_Intel
Employee
97 Views

Hi,

 

As I understand it, you have some inquiries related to an example design on CV Native PHY. To ensure we are on the same page, would you mind to further elaborate on the specific design that you are referring to? For example, the cv XCVR file page that you mentioned in your initial description would be helpful for us to understand the specific design.

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

CheePin_C_Intel
Employee
97 Views

Hi,

 

As I understand it, you have open a separate case 04471430 which seems to be similar to this. For better tracking purpose, I would like to recommend that we use the current thread for subsequent discussion.

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

 

NShah22
Beginner
97 Views

Thanks Chee pin for your quick response.

 

I need to send/receive 16 bit data using cyclone V Native PHY with 8b/10b encoding and manual alignment. is there some reference design for this data transmission.

 

Thanks

Nibandh

CheePin_C_Intel
Employee
97 Views

Hi,

 

Thanks for your clarification. As I understand it, you are looking for example design with 16 bit interface-width Native PHY with 8b10b encoding enabled and manual alignment.

 

For your information, I have search into our data base and found the following simulation example which was previously available in wiki which might be helpful for you to have a quick start. I have sent the ZIP to you at your email. The following are some description of the example design for your reference:

 

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Cyclone V Native PHY with manual alignment, 8b10b enabled and byte ordering in single width mode design example

 

This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Native PHY with manual alignment, 8b10b enabled and byte ordering in single width mode. The purpose of this design example is to assist users to have quick start with the Cyclone V transceivers. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The design consist of only one transceiver channel with fixed 16 bits data pattern. In the test bench, the MSByte and LSByte of the data pattern are purposely swapped half way during simulation to show the byte ordering occurrence in case the correct byte ordering has been achieved directly after word alignment. Note that you should create your word alignment and byte ordering controller as the controls are done in test bench in the example.

 

To run the simulation, do the following:

 

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

 

---------

 

Please let me know if there is any concern. Thank you.

rzhan64
Beginner
97 Views

hi,Can you also send one to me?

thank you very much

 

 

CheePin_C_Intel
Employee
97 Views

Hi, For your information, the system seems to only allow me to send the files to the one who open the case. Would you mind to open a new Forum case so that I could send the files to you? Thank you very much. Best regards, Chee Pin
NShah22
Beginner
97 Views

Hi,

 

I received the reference design in my mail.

 

Thank you

 

Nibandh

CheePin_C_Intel
Employee
97 Views

Thanks for the update.

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