I have a test design consisting of a Qsys-based PCIe core and some test logic. I am developing this using the Cyclone IV GX transceiver starter kit, with Jungo WinDriver on the PC. I have been able to read and write registers mapped to a BAR space of my design. I have not been able to generate interrupts successfully.
Every second, my test logic sets an internal FF to 1. It is reset by a write to a "clear interrupt" register in the BAR space. I exported the FF state to an LED, so I could verify that it is set every second, and can be reset by writing to the BAR register using the driver wizard software. That works fine.
The output of the FF is also routed to IRQ0 of the PCIe IP. If I check the PCIe interrupt status register at 0x0040 in the CRA space (which is mapped to memory space on the PCIe bus), I see bit 0 gets set every second. I have the interrupt enable register at 0x0050 in the CRA space set to 0xffff. In the driver wizard, I have it set to write to the "clear interrupt" register. When I select "listen to interrupts", I do not get any interrupts logged, and I do not see any activity on the interrupt pending LED.
Besides enabling the interrupts in the IER register at 0x0050, is there anything else I need to do to enable interrupts?
