How can I use Altera's HP DDR controller for fast 8x64 read?

[Altera_Forum]

Hi,  

 A newbee's question. Needs suggestion and confirmation.  I have an application in SOPC. There are 2-3 masters that need to access a DDR SRAM. The data width for all masters are 64bits. The DDR width is 16bits (will be 32 in the future). The controller works at half rate. The controller is connected to DDR SRAM through Avalon MM bus in SOPC.  One of the masters needs to read 8 continuous 64 bit words at a time from DDR. As I read Altera's HP DDR controller spec, I can only set the burst  width to 1. So, it seems that burst mode does not work. Currently, it takes many clocks (>22) for each 64 bits reading. It seems that I need to make the the process work in pipeline mode  in order to reduce average clock cycles needed. But how?   Do I need to create a FIFO in my application to store up to 8 reading result?  What Avalon signal should I use? readdatavalid, waitrequest)?  Any reference design?  How many clocks does full 8x64 reading process take (expected), when only this master is accessing DDR?  Thanks,  Kevin

[Altera_Forum]

You can configure your masters to do bursts of 8. SoPC builder will automatically add burst adapters between your masters and the DDR controller (which only does a burst of 2). If that doesn't take care of it, you could add a single pipeline bridge between all the masters and the DDR controller. This may improve performance at the expense of higher latency. 

 Jake

[Altera_Forum]

Jake, 

 Thanks for your suggestion. I have tried adding an pipeline bridge.  However, it takes ~26 clks for each reading. 8 reading takes 8x26 = ~ 208 clks. My understanding is that pipeline allows another reading  starts without receiving readdata_valid for the earlier reading request.  Have I set something wrong?  Best,  Kevin

[Altera_Forum]

The pipeline bridge should allow you to make as many read requests as you've specified in configurations without making you wait. 

 I don't know what your masters look like but I assume they are pipelined. If your master is not pipelined, there is no way you are going to get any kind of efficiency out of the controller. I have seen the DDR controller get up to 95% efficiency on reads.  Jake

[Altera_Forum]

Bursting will allow your master to lock down the arbiter for the duration of the burst. You can also increase the arbitration share of your master which will allow it to keep accessing the slave port assuming it doesn't de-assert the read or write signals. 

 This document will provide more details: http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf