Hello,I am trying to port an old design to the Arria V GX Starter Kit development board. The old design had a 64-bit AXI3 interface to a custom DDR2 controller but now I need to port it to the board which uses DDR3. I generated a DDR3 controller with UniPHY but it has an Avalon memory mapped interface. I couldn't find any components in Qsys that allows me to connect an AXI master to this Avalon interface. The only components available to me are AXI Master Agent, AXI Slave Agent, and AXI Translator which doesn't give me the AXI-to-Avalon functionality I need. How do I do this? Thanks, Lloyd
How do I do the connection? If you look at the attached JPEG, I have a DDR3 Uniphy Controller and an AXI Master component. None of the ports on the modules can connect to each other. The AXI Master component has an Avalon streaming interface while the DDR3 controller has a memory-mapped interface. I have tried every AXI module available and none of them seem to provide the proper connections to the controller. How did you do it?
that's interesting, if you instantiate the Hard Processor System the AXI bus will connect to the DDR3 MM slave, but the AXI Master Agent will not. i'm guessing this may be a bug in the AXI Master Agent?
i take that back, the AXI Master Agent component only has an AXI slave interface. change to an AXI Slave Agent, and you'll be able to connect to an MM slave
Thanks for the tip about the slave but that didn't work either (see attached JPEG). I instantiated the AXI slave and connected its master interface to the Avalon MM port on the DDR3 controller. However, I am not able to export the AXI interface to my external logic so it can talk to the controller. If I click on the "HDL Example" tab in Qsys, I don't see an AXI interface that my logic can connect to. If I try exporting the AXI master interface, then the thick, black line that connects the slave's AXI master interface to the DDR3 controller's Avalon interface goes away.
ok i see. as mentioned, I haven't used any of the AXI Agents, just the Hard Processor Systemyou can't use a bus internally in Qsys and also export it. maybe the AXI Translator is what you need. connect the AXI Master to the MM Slave, and export the AXI Slave