FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

How do I use HDL import in Dsp Builder?

Altera_Forum
Honored Contributor II
‎10-08-2009 04:18 PM
1,470 Views

I have performed 'compile' in quartus II of a serial/parallel converter block with good results. When importing my VHDL code to simulink/Dspbuilder by means of HDL import, the clock pin didn't show up.  

 

Hence, for a bit stream at the block input, I didn't observe any parallel data output. In fact I've tried various sample times in the PLL block.  

How can I handle this this observe the same results as in Quartus II?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.