I have performed 'compile' in quartus II of a serial/parallel converter block with good results. When importing my VHDL code to simulink/Dspbuilder by means of HDL import, the clock pin didn't show up.
Hence, for a bit stream at the block input, I didn't observe any parallel data output. In fact I've tried various sample times in the PLL block. How can I handle this this observe the same results as in Quartus II?