How effective is the video Frame Buffer core when storing in memory?

[MoZdk]

The Video and Image Processing (VIP) Suite IP has a Video Frame Buffer (VFB) core, named Frame Buffer II IP Core, that can take streaming images on the Avalon-ST IF and save it into memory using Avalon-MM IF, for using a DDR3 memory controller.

In my application, the VFB Frame Buffer II IP Core has these interfaces:

- Streaming video: Avalon-ST IF width 48 bits (for 2 pixels in parallel of each 24 bits)

- Memory interface: Avalon-MM IF width 64 bit

Since the memory bandwidth is critical, I want to determine the expected amount of overhead, but I am unable to find any information about this in the "Video and Image Processing Suite User Guide (UG-VIPSUITE | 2021.02.12)".

So, how effectively does the VFB Frame Buffer II IP Core pack the 48-bit Avalon-ST IF data into the memory using the 64-bit Avalon-MM IF ?  For example, is the 48 bit Avalon-ST data packed back-to-back in memory, or is the 48-bit Avalon-ST data aligned to the 64-bit Avalon-MM data size, thereby introducing an overhead of 33 %.

[MoZdk · Accepted solution]

The information is in document ""Video and Image Processing Suite User Guide (UG-VIPSUITE | 2021.02.12)" section "16.7.3. Memory Map for Frame Reader or Writer Configurations" paragraph "The frame data is tightly packed into memory and aligned on frame (or field) boundaries to minimize storage usage and maximize memory bandwidth usage."

So the data is tightly packed in memory.

[MoZdk]

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[ZH_Intel]

Hi MoZdk,

Usually memory bandwidth(efficiency) is 90% with increment address, but bandwith will drop to 50% with random address.

May I know the memory interface Avalon clock frequency and video stream Avalon clock frequency?

Best Regards,

Zul

[MoZdk]

Hi Zul,

The frequencies are pretty moderate with DDR3 at 400 MHz and video pipe at 112.5 MHz in a Cyclone V device, with pixel rate of 2 per cycle.

As I noted, the question was answered based on the reference I made above, with information about how the VFB stores data on the Avalon-MM IF.  That will be linear, but for best efficiency then Bank-Row-Column mode must be used in the DDR3, with frame spacing that ensure different frames goes in different banks, to benefit from open row on both write and read side of the VFB.

Best regards MoZdk