How efficient is DSP builder ?

[Altera_Forum]

Hi all, 

 In the year 2001 I witnessed the start of Xilinx Matlab blocksets, I tried them in my project, it was absolute failure so I abandoned them and went manual.  Later Altera produced their own(DSP builder) based on Matlab platform.  The idea of using any design acceleration is attractive to managers but has its own negative effects on designers.   I notice from this forum that many people are using DSP-builder. I would like to ask the actual design engineers(not the students) as how much weight they give to these tools. I know in some cases they give you a quick solution but they can't cover a wide range of cases e.g. you can design an FIR filter quickly(this easy anyway) but not FIR filters in multi-rate,multi-channel, TDM-based systems or even control its gain.  Away from any commercial bias, am I right?  Thanks  Kaz

[Altera_Forum]

I am more impressed with the Synplify DSP product than I am with the Altera DSP product. Altera is coming out with an Advanced blockset that will allow you to do multi-rate filters. 

 In general, if you are happy with what a megafunction will give to you - then that is exactly what Altera builds. If you need more than that - coding by hand is the way to go.  Personally, I've coded everything by hand that ends up in a product. I am interested in the "import HDL" option in the Altera DSP blocks to perform accelerated simulations on a target platform, but it croaked on my HDL that was synthesizable in Quartus II.

[Altera_Forum]

Hi, 

 Well you confirmed my thoughts. I don't think that these tools are yet part of the design engineer's culture but they are so common here on the forum. I believe students are misled into the wrong direction. You can see most of the posts are about tool-related problems and compatibility isssues.  As to specific Altera cores such as fft/NCO...etc then they are very useful generally and are in common use but even then some engineers prefer to do their own as these cores are not always portable or transparent and could be rigid as well as counter-intuitive.  Recently a new tool appeared (C to FPGA compiler) that targets fpga design without going through HDL and is meant for DSP engineers. It also targets specific technology.  It is getting really nasty when it comes to all these tools trying to compete yet extensive hand-made HDL design will always be needed at some point within the system after all.  The issue is not against using other's work. We all work as a team and our modules have to interface with each other. The problem is more to do with the commercialisation and subsequent complexity of parameters, of GUI,of documentation...etc.  Kaz

[Altera_Forum]

To add to the catalogue of mess, LabView to FPGA design tool has been released recently. It bypasses HDL design. Welldone! 

 What else is going to be added to this infinite messy list of profit-makers? possibilties include: barking-to-fpga deign...  The goooood news is that FPGAs are great, everybody targets them. At the end substantial Field HDL is inevitable.  kaz

[Altera_Forum]

DSP Builder has gotten alot better. Of course, hand coding will always beat automatic code generation... (assuming you know what you're doing... otherwise, DSP Builder is a lot easier)...

[Altera_Forum]

I'm using DSP Builder for implementing morphological operators in an R&D industrial project based on thermographical image processing. The results achieved un simulation are quite good. 

 At this moment I'm trying to integrate my custom hardware DSP blocks in my system using Cyclone III NIOSII evaluation kit. But I'm having some troubles by using DMA controllers for sending data from memory to the DSP blocks.

[Altera_Forum]

I would probably do the following: 

 - Surround your DSP Builder design with a pair of Avalon MM (or streaming) interfaces, depending on your design - Then create a SOPC Builder system and import your DSP Builder component into system in SOPC Builder - Then add the DMA Controller in SOPC Builder...  - possibly create some sort of Nios II controller to control the data flow...

[Altera_Forum]

1.- I use Avalon FIFO-MM Wr/Rd slaves in DSP builder 

2.- I use two master DMA controllers in SOPC Builder conected to their respectives slaves in order to write and read processed data after DSP cycles. 3. I call to HAL API DMA routines to start DMA Cycles but now I'm hanged at this point.

[Altera_Forum]

All good dialogue. 

 Reminds me of the days when we all debated the Assembly .vs. PLM .vs. C code debates.  Then there was the debate of if a processor should PUSH / POP all the registers or just the ones you are going to use when servicing an interrupt.  Or how "good" auto routers were in Routing PCB designs.  Then it transitioned to the Schematic .vs. HDL .vs. Celoxica Handel C .vs. etc, etc, etc debates.  Customer Hand crafted code will always (never say always) be tighter and more efficient than "tool" generated results (in theory).  If you have something that takes "1" unit of time or quality of efficiency now, and desire to have a 10x improvement, nd a tool like DSP Builder will give you 12x -15x, you are done. If you need 100x, then you will need to hand code it.  I too used the Xilinx System Generator (for DSP) in it's day.  I also use the Altera DSP Builder (and now Advanced BLockset).  Much inprovment has occured since the early days. Is it perfect - or done - not yet.  Will any of these replace "understanding what you need to do first" - NO.  Let's hear from more users in this community on the topic.  Thanks for starting this thread, Kaz.  Avatar

[Altera_Forum]

I assume you have a NIOS II soft processor in your SOPC System as well right? I would check the connections in SOPC Builder or check your Nios II code. But I think at this point, it's moved beyond DSP realm... it's more of a Nios/SOPC related issue.... Since I am not exactly an expert in Nios/SOPC Builder, I would suggest posting at the niosforum and see if you can get some more help.

[Altera_Forum]

I've a NIOS within my system. I've attached a picture of connections of DMA controllers and DSP hardware in SOPC Builder. 

 the cycle would be:  1. Control ports of both DMA are connected to the NIOS Data Master bus.  2. DMA Loader reads data from array located in DDR and sends data to Wr slave DSP custom block.  3. DMA store reads data from Rd slave DSP custom block and sends data to array located in DDR.   I'll continue working in order to solve this problem.  thanks anyway

[Altera_Forum]

I prefer to think about possible solutions before using the tool. It may be possible use simple concatenated filters based on shift and adds or subtracts to implement what you want, especially if you have some freedom of choice in what is acceptable ripple or cutoff. 

 Nothing replaces a little bit of thought up front, but if the solution is not apparently simple by all means resort to the tool and save yourself a lot of time.  Mind you, I still use assembler too; you can probably guess my age, its my birthday today.