FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

How to configure DisplayPort TX to support BT.2020 colorimetry

petr_simi
Beginner
334 Views

Hi everyone,

we are not able to configure DisplayPort TX to use BT.2020 colorimetry.

 

Let's say we want to transmit YCbCr 4:2:2, 10 bit, limited range, BT.2020.

According to the DisplayPort 1.4 specification we set MISC0 and MISC1:

 

 DPTX0_MSA_MISC1

  • bit 6 = 1 (Use VSC SDP)

 

MISC0 should be ignored now, but we still set it, e.g:

DPTX0_MSA_MISC0:

  • bits 7-5: 010 (10 bit)
  • bit 4: 1
  • bit 3: 0
  • bit2-1: 01 (4:2:2)

 

DPTX0_MSA_COLOR:

  • bit 13: 1 (use VSC SDP)
  • bit 12: 1 (CEA range)
  • bits 11-8: 0111 (BT.2020 YCbCr)
  • bits 7-4: 0010 (YCbCr 4:2:2)
  • bits 2-0: 010 (10 bits)

 

we also call Bitec function:

 

btc_dptx_set_color_space(0 /*instance*/, 2 /*YCbCr 422*/, 2 /*10bits*/, 1 /*limited range*/ , 7 /*bt2020*/, 1 /*use VSC SDP*/);

 

Basic colorimetries (BT609 and BT709) and color spaces (RGB, YCbCr 422/444) works well, when we use MISC0 instead od VSC SDP.

 

Using Quartus Pro 19.1

 

petr_simi_0-1600763045232.png

 

 

Can you please advice how to put BT2020 into operation?

 

Thank you,

Petr

0 Kudos
1 Solution
Deshi_Intel
Moderator
315 Views

HI,


You are right in the sense that BT.2020 should be enabled via VSC SDP but I don't see you enable "secondary data channel" in your Intel DP Tx IP.

  • This could be the problem as you are transferring secondary data packet (SDP) here


Below is what I found out from DP rev1.4 spec

  1. Pre-requisite
  • Ensure DP sink EDID support 3D Stereo in-band signaling
    • Ensure DP sink enable “VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED”, DPCD address 0x2210h (bit 3 = 1)  
    • Enable Intel DP Tx “secondary data channel”
  • Then to enable/configure BT.2020 support
    • DP Tx set MSA (MISC1, bit6 =1) to use VSC SDP
    • Configured YCbCr 422 BT.2020 setting via VSC SDP, payload data byte (DB16)


Thanks.


Regards,

dlim


View solution in original post

1 Reply
Deshi_Intel
Moderator
316 Views

HI,


You are right in the sense that BT.2020 should be enabled via VSC SDP but I don't see you enable "secondary data channel" in your Intel DP Tx IP.

  • This could be the problem as you are transferring secondary data packet (SDP) here


Below is what I found out from DP rev1.4 spec

  1. Pre-requisite
  • Ensure DP sink EDID support 3D Stereo in-band signaling
    • Ensure DP sink enable “VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED”, DPCD address 0x2210h (bit 3 = 1)  
    • Enable Intel DP Tx “secondary data channel”
  • Then to enable/configure BT.2020 support
    • DP Tx set MSA (MISC1, bit6 =1) to use VSC SDP
    • Configured YCbCr 422 BT.2020 setting via VSC SDP, payload data byte (DB16)


Thanks.


Regards,

dlim


Reply