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How to generate a design in verilog with DSP Builder and Simulink

Altera_Forum
Honored Contributor II
‎11-30-2009 06:32 PM
1,485 Views

Hi all, 

 

I use Matlab->SIMULINK to design a system (with DSP Builder). I generate the .vhdl but I don't know how to make the .v . I don't find the option to generate the .v.  

Someone does have an idea please ?  

 

Best regards, 

 

Jeremy.:confused:
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Altera_Forum
Honored Contributor II
‎12-01-2009 08:34 AM
336 Views

DSP Builder only generates VHDL files. There is now way to generate verilog files I'm afraid.

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Altera_Forum
Honored Contributor II
‎12-01-2009 09:47 AM
336 Views

Hi, 

 

Thank you for your answer :) 

 

Best regards. 

 

Jeremy.
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