Let me explain my problem. Im going to connect Arria10 FPGA with MTA72ASS8G72LZ. In this case, hard phy has only one signal ODT, while memory has two ODT inputs. User guide says that one is ok, but it is true? In additional other vendor memory phy has 2 ODT signals in the same configuration.
Yes, this is true. You can use one ODT from FPGA connect to 2 ODT on the same DIMM. Using balanced tree topology.
To explain further why we only need one. The reason is because for LRDIMM, the data bus is buffered. So the CS will already disable the other rank data buffer. Even you turn on ODT or not to the other rank, it will not take any effect to data bus.