I come across a problem about pll

[Altera_Forum]

I use the ep2s60 mini-board.when 50Mhz clock is devided into 25Mhz and 10Mhz,I find that the high level of 25Mhz clock is 1.8 v but 10MHz is 3.3v by oscillograph .Why:confused:? 

Thank anyone who freeback on my post!:)

[Altera_Forum]

The PLL and it's output clocks are completely unrelated to voltage levels. Those clocks are generated internal to the chip. Apparently you have chosen to output those clocks on the FPGAs I/O pins (or maybe dedicated clock output pins). In such a case, the output voltage level will correspond to whatever value of VCCIO you have for that I/O bank.  

 So, your 25Mhz clock is being put out on an I/O bank with 1.8V VCCIO and your 10MHz clock is being put out on an I/O bank with 3.3V VCCIO.

[Altera_Forum]

Thank you for your reply,jakobjones.I'm a beginer.If I want to get 25Mhz clock with 3.3 v,can I put out on the 3.3v IO instead of pllout? 

noisor

[Altera_Forum]

You can drive a clock out on any general purpose I/O. The PLL clock output pins have dedicated circuitry to provide a low-jitter clock output. 

 Jake