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Honored Contributor I
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I have some questions!

Hi,I am now useing the triple-speed ethernet Megacore,I have a questions about the control interface,the IP core have 8-bit address,but the mac interface register Map have 12-bit address offset,so how can I access the high 4-bit space? thank you!

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Honored Contributor I
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the mac interface register Map have 12-bit address offset 

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They are actually spanning a 10-bit range. 

 

The IP handbook clarifies: 

 

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8-bit address signal, which provides access to 256 32-bit registers 

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Obviously the address map shows byte addresses, all addresses are multiples of four. So byte address[1..0] are implicitely zero.
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Honored Contributor I
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Thank you for your reply! 

I want to ask you another question,Now I have added a control module to the MAC's avalon slave interface,I found that the out signal readdata[31..0] have nothing out,so I set the control module'sclk(5MHz) five times slower than the MAC clk(25MHz) input,the out signal readdata[31..0] have some thing out,but ,they are not what I want ? and the signal waitrequest changed several times ,then it gone to high,not to jump any more! 

So ,I want to know how to exactly use the avalon slave interface?
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Honored Contributor I
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What do you mean, the Avalon-ST data path interface or the Avavlon-MM control interface? There are detailed interface specifications for both with the SOPC builder documentation.

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Honored Contributor I
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Did you properly reset the MAC? Does it receive the clock from the MII side too? 

It needs several cycles after reset before it is ready. In that case the waitrequest signal will be asserted.
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