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Implementation of Avalon ST-Video protocol

Altera_Forum
Honored Contributor II
848 Views

Hello, 

I try to implement a Avalon ST-Video Interface in a component inside a video and image processing chain.  

The chain I use (from tPad VIP Camera example) works without my component. The present processing chain is : Clocked Video Input/Color Plane Sequencer/Frame Buffer/Clipper/Scaler/Mixer/Control Synchronizer/Frame Buffer/Color Plane Sequencer/Clocked Video Input. It uses camera's frames and displays them on a screen.  

For now, in order to learn how use this interface, my goal is just to have with my component a delay of one cycle between the Clocked Video Input and the Color Plane Sequencer.  

Here is my VHDL code : 

 

 

--- Quote Start ---  

 

asi_in0_ready <= aso_out0_ready; 

 

process(clk) 

begin 

 

if clk'event and clk='1' then 

if asi_in0_valid='1' and aso_out0_ready='1' then 

aso_out0_valid <= asi_in0_valid; 

aso_out0_data <= asi_in0_data; 

aso_out0_startofpacket <= asi_in0_startofpacket; 

aso_out0_endofpacket <= asi_in0_endofpacket; 

else 

aso_out0_valid <= '0'; 

end if; 

end if; 

 

end process; 

 

--- Quote End ---  

 

 

The problem is just the first frame is displayed on the screen and after it is freezed. I don't understand what is wrong. Could someone help me? 

Thank you in avance,
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
85 Views

does your core propagate ready upstream? don't forget the video IP has a ready_latency=1

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